Cadence-Based Modeling and Performance Evaluation of a Dual-Gate Tunnel FET for Low-Power VLSI Applications
DOI:
https://doi.org/10.46610/IJESVD.2026.v02i02.003Keywords:
Al2O3, Cadence, DG-TFET, InAs, Power dissipation, Subthreshold swingAbstract
The aim of this work is to investigate a simulation-centric performance analysis of an ultra-scaled dual-gate tunnel FET (DG TFET) in the Cadence simulation environment. The investigated TFET structure has a channel length of 20 nm and uses high-mobility InAs as the channel material and high-K Al2O3 as the oxide material. InAs as the channel material. This research simulated a Verilog-A-based model of a DG Tunnel FET using the Virtuoso tool of Cadence to assess its better performance than traditional 45nm TSMC-based transistors. The model is modified to suppress the undesirable ambipolar conduction, which is a characteristic feature of conventional TFETs, to explore the potential of the investigated FET in VLSI circuits. The characteristic curves obtained from the Cadence simulation demonstrate a sub-0.3 V threshold voltage, nA-order OFF current, μA-order ON current, a high value of transconductance, and subthreshold swing slightly lower than the theoretical Boltzmann minimum. All these features, therefore, confirm the potential use of DG TFETs in low-power, ultra-scaled VLSI applications.
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