International Journal of Embedded System and VLSI Design

A Comprehensive Survey of Low-Power and High-Stability SRAM Architectures for Scaled CMOS Technologies

2026-09-03T04:43:58+00:00

Static Random Access Memory (SRAM) remains a dominant on-chip memory technology in modern VLSI systems; however, CMOS scaling introduces challenges such as increased leakage, reduced noise margins, write instability, and process variations, limiting the reliability of conventional 6T SRAM at low voltages. This article presents a comprehensive survey of low-power and high-stability SRAM architectures across technology nodes from 180 nm to advanced 3 nm FinFET and GAA technologies. The survey reviews 6T, 8T, 9T, 10T, and Schmitt Trigger-based SRAM architectures using key metrics including RSNM, WNM, DRV, delay, power, leakage, and area. Techniques such as read/write decoupling, dual-Vt assignment, power gating, body biasing, near-threshold operation, data encoding, and Compute-in-Memory (CIM) are analyzed. Emerging technologies including FinFET, VNW-TFET, and hybrid GAA-FinFET are also examined. The analysis shows that 6T provides superior area and speed efficiency, while 8T offers improved read stability through path decoupling. 9T and 10T further enhance write margin and retention at increased area cost. Power gating combined with near-threshold operation and body biasing provides effective leakage reduction. The survey also highlights process-variation-aware design and silicon validation as key challenges for future SRAM technologies.

Secure Embedded Signal Processing Using Blockchain and Trusted Execution Environments

2026-09-19T06:49:29+00:00

Embedded signal processing systems, ranging from industrial sensors and medical wearables to programmable logic controllers, increasingly operate in physically exposed and network-connected environments where both the confidentiality of acquired signals and the integrity of processing results are at risk. Conventional software-only defenses cannot withstand adversaries who gain a foothold on the device operating system, while purely cryptographic protections often impose computational costs unsuitable for resource-constrained hardware. This article examines a hybrid security architecture that combines Trusted Execution Environments (TEEs), which provide hardware-isolated, attestable computation on the device itself, with blockchain technology, which provides a tamper-evident, distributed ledger for recording provenance and integrity proofs across untrusted networks. The architecture is presented alongside a review of the underlying building blocks, including ARM TrustZone and Intel SGX, encrypted-domain signal processing, remote attestation, and TEE-assisted blockchain consensus mechanisms. The article provides a comparative analysis of TEE technologies, known vulnerability classes, TEE-blockchain integration systems, and secure signal processing approaches, while synthesizing system architectures, processing pipelines, and consensus integration mechanisms. The article concludes by identifying open challenges in scalability, side-channel resilience, and standardization that must be addressed before such hybrid architectures can see widespread industrial deployment.

Cadence-Based Modeling and Performance Evaluation of a Dual-Gate Tunnel FET for Low-Power VLSI Applications

2026-11-02T07:00:43+00:00

The aim of this work is to investigate a simulation-centric performance analysis of an ultra-scaled dual-gate tunnel FET (DG TFET) in the Cadence simulation environment. The investigated TFET structure has a channel length of 20 nm and uses high-mobility InAs as the channel material and high-K Al₂O₃ as the oxide material. InAs as the channel material. This research simulated a Verilog-A-based model of a DG Tunnel FET using the Virtuoso tool of Cadence to assess its better performance than traditional 45nm TSMC-based transistors. The model is modified to suppress the undesirable ambipolar conduction, which is a characteristic feature of conventional TFETs, to explore the potential of the investigated FET in VLSI circuits. The characteristic curves obtained from the Cadence simulation demonstrate a sub-0.3 V threshold voltage, nA-order OFF current, μA-order ON current, a high value of transconductance, and subthreshold swing slightly lower than the theoretical Boltzmann minimum. All these features, therefore, confirm the potential use of DG TFETs in low-power, ultra-scaled VLSI applications.

A Controlled Benchmark Ablation of Fréchet-Window Battery Early Warning and Global Routing

2026-11-03T11:36:36+00:00

Researchers often propose candidate algorithms for embedded monitoring and routing with added machinery, such as windowed curve-similarity measures or iterative rerouting, before testing their value; hardware testing or labelled field data collection is slow and, for battery faults, hazardous. This article presents a synthetic-benchmark screening of two such designs, with explicit hypotheses and outcomes. Study A examines early warning of a simulated battery thermal-runaway precursor. Eight detectors, including an instantaneous voltage-temperature distance, a persistence rule, Fréchet windows, and an open-end Fréchet variant, were compared in five healthy-data scenarios, calibrated to about 2% false alarms, with 200 fault trials per setting. A robustness study added step and intermittent faults, heavy-tailed noise, and a local-outlier-factor baseline. The study proves that, for first-crossing alarms, a standard Fréchet window is exactly equivalent to the instantaneous distance; thresholds, false alarm counts, and median latencies were identical in all scenarios. The open-end variant was up to 1.1 s slower, and the local-outlier-factor baseline was slower than all simpler detectors. Persistence was decisive under heavy-tailed noise, detecting 199 of 200 one-degree steps against 42 for the instantaneous distance and Fréchet windows. Study B examines global routing on 20 × 20 and 32 × 32 grids. Rip-up and reroute removed all overflow in 15 of 15 netlists at 55% utilization and halved overflow at 85% relative to a congestion-aware single pass (paired Wilcoxon p < 0.001); a negotiated-congestion variant performed similarly. All data are synthetic. The results show where added complexity does not pay and provide a reusable benchmark and protocol for real-data testing.