Secure Embedded Signal Processing Using Blockchain and Trusted Execution Environments

2026-09-19T06:49:29+00:00

Embedded signal processing systems, ranging from industrial sensors and medical wearables to programmable logic controllers, increasingly operate in physically exposed and network-connected environments where both the confidentiality of acquired signals and the integrity of processing results are at risk. Conventional software-only defenses cannot withstand adversaries who gain a foothold on the device operating system, while purely cryptographic protections often impose computational costs unsuitable for resource-constrained hardware. This article examines a hybrid security architecture that combines Trusted Execution Environments (TEEs), which provide hardware-isolated, attestable computation on the device itself, with blockchain technology, which provides a tamper-evident, distributed ledger for recording provenance and integrity proofs across untrusted networks. The architecture is presented alongside a review of the underlying building blocks, including ARM TrustZone and Intel SGX, encrypted-domain signal processing, remote attestation, and TEE-assisted blockchain consensus mechanisms. The article provides a comparative analysis of TEE technologies, known vulnerability classes, TEE-blockchain integration systems, and secure signal processing approaches, while synthesizing system architectures, processing pipelines, and consensus integration mechanisms. The article concludes by identifying open challenges in scalability, side-channel resilience, and standardization that must be addressed before such hybrid architectures can see widespread industrial deployment.

A Comprehensive Survey of Low-Power and High-Stability SRAM Architectures for Scaled CMOS Technologies

2026-09-03T04:43:58+00:00

Static Random Access Memory (SRAM) remains a dominant on-chip memory technology in modern VLSI systems; however, CMOS scaling introduces challenges such as increased leakage, reduced noise margins, write instability, and process variations, limiting the reliability of conventional 6T SRAM at low voltages. This article presents a comprehensive survey of low-power and high-stability SRAM architectures across technology nodes from 180 nm to advanced 3 nm FinFET and GAA technologies. The survey reviews 6T, 8T, 9T, 10T, and Schmitt Trigger-based SRAM architectures using key metrics including RSNM, WNM, DRV, delay, power, leakage, and area. Techniques such as read/write decoupling, dual-Vt assignment, power gating, body biasing, near-threshold operation, data encoding, and Compute-in-Memory (CIM) are analyzed. Emerging technologies including FinFET, VNW-TFET, and hybrid GAA-FinFET are also examined. The analysis shows that 6T provides superior area and speed efficiency, while 8T offers improved read stability through path decoupling. 9T and 10T further enhance write margin and retention at increased area cost. Power gating combined with near-threshold operation and body biasing provides effective leakage reduction. The survey also highlights process-variation-aware design and silicon validation as key challenges for future SRAM technologies.

International Journal of Embedded System and VLSI Design

Secure Embedded Signal Processing Using Blockchain and Trusted Execution Environments

A Comprehensive Survey of Low-Power and High-Stability SRAM Architectures for Scaled CMOS Technologies