https://matjournals.net/engineering/index.php/IJESVD en-US International Journal of Embedded System and VLSI Design https://matjournals.net/engineering/index.php/IJESVD/article/view/4064 <p><em>Static Random Access Memory (SRAM) remains a dominant on-chip memory technology in modern VLSI systems; however, CMOS scaling introduces challenges such as increased leakage, reduced noise margins, write instability, and process variations, limiting the reliability of conventional 6T SRAM at low voltages. This article presents a comprehensive survey of low-power and high-stability SRAM architectures across technology nodes from 180 nm to advanced 3 nm FinFET and GAA technologies. The survey reviews 6T, 8T, 9T, 10T, and Schmitt Trigger-based SRAM architectures using key metrics including RSNM, WNM, DRV, delay, power, leakage, and area. Techniques such as read/write decoupling, dual-Vt assignment, power gating, body biasing, near-threshold operation, data encoding, and Compute-in-Memory (CIM) are analyzed. Emerging technologies including FinFET, VNW-TFET, and hybrid GAA-FinFET are also examined. The analysis shows that 6T provides superior area and speed efficiency, while 8T offers improved read stability through path decoupling. 9T and 10T further enhance write margin and retention at increased area cost. Power gating combined with near-threshold operation and body biasing provides effective leakage reduction. The survey also highlights process-variation-aware design and silicon validation as key challenges for future SRAM technologies.</em></p> Aditya Jaiswal J. Chandana Monica Singh S. Monoddin K. Vikash Kumar Copyright (c) 2026 International Journal of Embedded System and VLSI Design 2026-09-03 2026-09-03 1 13