International Journal of Embedded System and VLSI Design https://matjournals.net/engineering/index.php/IJESVD en-US International Journal of Embedded System and VLSI Design Python/Silvaco-based Performance Simulation and Quantum Analysis of a 14 nm Si/Si3N4 Cylindrical GAA FET https://matjournals.net/engineering/index.php/IJESVD/article/view/3080 <p><em>This study presents a comprehensive TCAD and Python-based simulation study of an aggressively scaled (channel length is only 14 nm) cylindrical Gate-All-Around Field-Effect Transistor (CGAA FET) featuring a silicon channel and Si</em><em><sub>3</sub></em><em>N</em><em><sub>4 </sub></em><em>high-</em><em>κ </em><em>gate dielectric. The CGAA structure enhances superior gate control, leading to the suppression of short-channel effects and hence, its lower power consumption, whereas Si</em><em><sub>3</sub></em><em>N</em><em><sub>4 </sub></em><em>increases the drive current, leading to its high-speed operation. </em><em>Using Silvaco ATLAS Technology Computer-Aided Design simulations with quantum mechanical models and postprocessing Python scripts, the device’s electrical performance, quantum confinement effects, and scalability was characterised. Key extracted parameters at </em><em>V</em><em><sub>DS </sub></em><em>= 0</em><em>.</em><em>05 V</em> <em>include a threshold voltage (</em><em>V<sub>T</sub></em><em>) of 0.32 V, subthreshold swing (SS) of 68.5 mV/dec, drain-induced barrier lowering (DIBL) of 36.7 mV/V, and an on/off current ratio (</em><em>I</em><em><sub>on</sub></em><em>/I</em><em><sub>off</sub></em><em>) of </em><em>7.8 × 10<sup>7</sup></em><em>. Detailed analysis of energy band diagrams, density of states, and wave functions confirms strong quantum confinement in the 3 nm thick channel. The GAA architecture demonstrates excellent electrostatic control, making it promising for sub-10nm CMOS technology nodes. </em></p> Md. Tawrath Md. Mohin Sarker Saif Rahman Md. Hojaifa Daiyan Chowdhury Md. Rashique Hamjah Chowdhury Muhammad Johirul Islam Iqbal Bahar Chowdhury Copyright (c) 2026 International Journal of Embedded System and VLSI Design 2026-02-07 2026-02-07 2 1 1 17 10.46610/IJESVD.2026.v02i01.001