International Journal of Embedded System and VLSI Design https://matjournals.net/engineering/index.php/IJESVD en-US International Journal of Embedded System and VLSI Design Python/Silvaco-based Performance Simulation and Quantum Analysis of a 14 nm Si/Si3N4 Cylindrical GAA FET https://matjournals.net/engineering/index.php/IJESVD/article/view/3080 <p><em>This study presents a comprehensive TCAD and Python-based simulation study of an aggressively scaled (channel length is only 14 nm) cylindrical Gate-All-Around Field-Effect Transistor (CGAA FET) featuring a silicon channel and Si</em><em><sub>3</sub></em><em>N</em><em><sub>4 </sub></em><em>high-</em><em>κ </em><em>gate dielectric. The CGAA structure enhances superior gate control, leading to the suppression of short-channel effects and hence, its lower power consumption, whereas Si</em><em><sub>3</sub></em><em>N</em><em><sub>4 </sub></em><em>increases the drive current, leading to its high-speed operation. </em><em>Using Silvaco ATLAS Technology Computer-Aided Design simulations with quantum mechanical models and postprocessing Python scripts, the device’s electrical performance, quantum confinement effects, and scalability was characterised. Key extracted parameters at </em><em>V</em><em><sub>DS </sub></em><em>= 0</em><em>.</em><em>05 V</em> <em>include a threshold voltage (</em><em>V<sub>T</sub></em><em>) of 0.32 V, subthreshold swing (SS) of 68.5 mV/dec, drain-induced barrier lowering (DIBL) of 36.7 mV/V, and an on/off current ratio (</em><em>I</em><em><sub>on</sub></em><em>/I</em><em><sub>off</sub></em><em>) of </em><em>7.8 × 10<sup>7</sup></em><em>. Detailed analysis of energy band diagrams, density of states, and wave functions confirms strong quantum confinement in the 3 nm thick channel. The GAA architecture demonstrates excellent electrostatic control, making it promising for sub-10nm CMOS technology nodes. </em></p> Md. Tawrath Md. Mohin Sarker Saif Rahman Md. Hojaifa Daiyan Chowdhury Md. Rashique Hamjah Chowdhury Muhammad Johirul Islam Iqbal Bahar Chowdhury Copyright (c) 2026 International Journal of Embedded System and VLSI Design 2026-02-07 2026-02-07 2 1 1 17 10.46610/IJESVD.2026.v02i01.001 Experimental Investigation of Attenuation and Chromatic Dispersion in Single-Mode Optical Fiber under Varying Environmental Conditions https://matjournals.net/engineering/index.php/IJESVD/article/view/3514 <p><em>This study presents an experimental investigation of attenuation and chromatic dispersion in single-mode optical fiber under varying environmental conditions, including temperature fluctuations and mechanical bending. The objective is to evaluate how these external factors influence signal degradation and overall transmission performance in modern optical communication systems. A dual-wavelength laser source operating at 1310 nm and 1550 nm was employed to transmit optical signals through a 10 km spool of standard Single-Mode Fiber (SMF-28). The fiber was subjected to controlled temperature variations within a programmable chamber and mechanical stress using a precision bending platform. Attenuation was measured using an optical power meter, while chromatic dispersion and signal integrity were analyzed using an Optical Time-Domain Reflectometer (OTDR). In</em> <em>addition, Bit Error Rate (BER) and eye diagram analyses were conducted to assess system-level performance. The experimental results indicate that attenuation increases with rising temperature and decreasing bending radius due to enhanced scattering and macro-bending losses. Chromatic dispersion was found to be wavelength-dependent, with minimum dispersion near 1310 nm and higher dispersion at 1550 nm. Furthermore, BER analysis revealed significant degradation in signal quality with increasing transmission distance, which was corroborated by progressive eye diagram closure. Overall, the findings highlight the critical impact of environmental conditions on fiber optic performance and emphasize the need for effective system design, proper installation practices, and compensation techniques to ensure reliable high-speed optical communication.</em></p> Md. Sumon Ali Md. Ali A. S. M. Shamim Hasan Syed Tohabbul Murshed Copyright (c) 2026 International Journal of Embedded System and VLSI Design 2026-05-04 2026-05-04 2 1 18 28 Lightweight Cryptographic Watermarking Architecture for Resource-Constrained IoT and Edge Devices https://matjournals.net/engineering/index.php/IJESVD/article/view/3523 <p><em>The proliferation of Internet of Things (IoT) ecosystems and edge computing infrastructures has created an urgent demand for security mechanisms capable of operating within the stringent resource constraints characteristic of embedded platforms—including limited computational capacity, minimal memory footprint, and severe power budgets. Conventional cryptographic watermarking schemes, designed for general-purpose computing environments, impose computational overhead that renders them impractical for deployment on microcontroller-class devices with clock frequencies below 100 MHz and available RAM of 64–512 KB. This paper proposes a novel Lightweight Cryptographic Watermarking Architecture (LCWA) specifically engineered for resource-constrained IoT and edge devices, integrating the PRESENT-80 lightweight block cypher with a computationally efficient Least Significant Bit Frequency Domain (LSBFD) watermarking scheme optimised through bitwise operations and lookup table acceleration. The architecture implements a pipeline processing model that overlaps cryptographic and watermarking operations, significantly reducing total processing latency compared to sequential execution. Hardware-software co-design principles are employed to identify and accelerate the computational hot-spots of both the cypher and watermarking algorithm through dedicated hardware acceleration units. The proposed architecture was implemented on an Xilinx Artix-7 FPGA and an ARM Cortex-M4 microcontroller platform for comprehensive evaluation. Results demonstrate that the proposed scheme achieves 98.7% of the security efficacy of full AES-256-DWT watermarking while consuming only 12.3% of the computational resources, 8.7% of the memory footprint, and 15.4% of the power consumption. The achieved throughput of 3.8 Mbps on the ARM Cortex-M4 platform at 168 MHz is sufficient for real-time protection of IoT sensor data streams.</em></p> Madhuri Mohanrao Karad Copyright (c) 2026 International Journal of Embedded System and VLSI Design 2026-05-07 2026-05-07 2 1 29 38