A Comprehensive Survey of Low-Power and High-Stability SRAM Architectures for Scaled CMOS Technologies
Keywords:
CMOS scaling, Compute-in-memory, Leakage reduction, Low-power memory, Near-threshold operation, Static noise margin, Static Random Access Memory (SRAM)Abstract
Static Random Access Memory (SRAM) remains a dominant on-chip memory technology in modern VLSI systems; however, CMOS scaling introduces challenges such as increased leakage, reduced noise margins, write instability, and process variations, limiting the reliability of conventional 6T SRAM at low voltages. This article presents a comprehensive survey of low-power and high-stability SRAM architectures across technology nodes from 180 nm to advanced 3 nm FinFET and GAA technologies. The survey reviews 6T, 8T, 9T, 10T, and Schmitt Trigger-based SRAM architectures using key metrics including RSNM, WNM, DRV, delay, power, leakage, and area. Techniques such as read/write decoupling, dual-Vt assignment, power gating, body biasing, near-threshold operation, data encoding, and Compute-in-Memory (CIM) are analyzed. Emerging technologies including FinFET, VNW-TFET, and hybrid GAA-FinFET are also examined. The analysis shows that 6T provides superior area and speed efficiency, while 8T offers improved read stability through path decoupling. 9T and 10T further enhance write margin and retention at increased area cost. Power gating combined with near-threshold operation and body biasing provides effective leakage reduction. The survey also highlights process-variation-aware design and silicon validation as key challenges for future SRAM technologies.
References
P. Athe and S. Dasgupta, "A comparative study of 6T, 8T and 9T decanano SRAM cell," 2009 IEEE Symposium on Industrial Electronics & Applications, Kuala Lumpur, Malaysia, 2009, pp. 889-894.
T. Singh, V. Prakash, S. S. Anwer, and G. Ahmad, "Analyzing the Performance of 6T SRAM Cell and 64×64 Memory Array at Lower Technology Nodes for Low Power Design," 2023 1st International Conference on Circuits, Power and Intelligent Systems (CCPIS), Bhubaneswar, India, 2023, pp. 1-6.
S. Kumar, R. K. Yadav, V. Singh, D. Kumar, D. Kumar, and S. Tyagi, "Technology Scaling Impact on 6T SRAM Cell: SNM & Power Analysis from 180 nm to 22 nm," 2025 5th International Conference on Advancement in Electronics & Communication Engineering (AECE), Ghaziabad, India, 2025, pp. 354-358.
T. Kalpana, C. L. Reddy, B. Saranya, and P. Naveen, "A Low Voltage 6T SRAM Cell Design and Analysis Using Cadence 90nm and 45nm CMOS Technology," 2024 7th International Conference on Devices, Circuits and Systems (ICDCS), Coimbatore, India, 2024, pp. 188–194.
B. Majumdar and S. Basu, "Low power single bitline 6T SRAM cell with high read stability," 2011 International Conference on Recent Trends in Information Systems, Kolkata, India, 2011, pp. 169-174.
S. Sharan, A. Chandra, N. Goel, and A. Kumar, "Comparison of 6T-SRAM cell designs using DTMOS and VTMOS for low power applications," 2016 IEEE 1st International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES), Delhi, India, 2016, pp. 1–5.
R. Krishnaraj, T. Senthil, N. Vikram, B. Soundarya, and A. Sharmila, "Design of a Sleep transistor and read, write separation based 6T SRAM Memory Array for Low Power IOT Applications," 2021 Smart Technologies, Communication and Robotics (STCR), Sathyamangalam, India, 2021, pp. 1–5.
S. Jalasutramsravanthi, S. Fareedbasha, G. Raviteja, and U. Bhagyasri, "Design and Analysis of Near-Threshold 6T SRAM Cell for Low Power Applications," 2025 5th International Conference on Artificial Intelligence and Signal Processing (AISP), Vijayawada, India, 2025, pp. 1–4.
S. K. Ojha, O. P. Singh, G. R. Mishra, and P. R. Vaya, "Analysis and design of single ended SRAM cell for low-power operation," 2016 11th International Conference on Industrial and Information Systems (ICIIS), Roorkee, India, 2016, pp. 178–181.
Hansraj, A. Chaudhary, and A. Rana, "Ultra Low power SRAM Cell for High Speed Applications using 90nm CMOS Technology," 2020 8th International Conference on Reliability, Infocom Technologies and Optimization (Trends and Future Directions) (ICRITO), Noida, India, 2020, pp. 1107–1109.
N. Monish and S. Roy, "Analysis of 6T, 7T, 8T SRAM Cells Using FinFET at 7nm Technology," 2025 International Conference on Frontier Technologies and Solutions (ICFTS), Chennai, India, 2025, pp. 1–6.
C. Zhou, Y. Zhang, Y. Zhao, and Z. Wang, "A New 8T SRAM Cell Design of Low-Power and High-Write-Speed," 2024 3rd International Symposium on Semiconductor and Electronic Technology (ISSET), Xi'an, China, 2024, pp. 473–476.
C. Roy, S. KM, V. Bijapur, and S. Joshi, "A Novel Power-Gating 8T SRAM Cell with Improved Standby and Operational Efficiency," 2025 21st IEEE International Colloquium on Signal Processing & Its Applications (CSPA), Pulau Pinang, Malaysia, 2025, pp. 266–271.
D. Anh-Tuan, J. Y. S. Low, J. Y. L. Low, Z.-H. Kong, X. Tan, and K.-S. Yeo, "An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, no. 6, pp. 1252–1263, June 2011.
G. Pasandi and S. M. Fakhraie, "An 8T Low-Voltage and Low-Leakage Half-Selection Disturb-Free SRAM Using Bulk-CMOS and FinFETs," IEEE Transactions on Electron Devices, vol. 61, no. 7, pp. 2357–2363, July 2014.
S. A. D. V. Jacinto et al., "Development of Low Power Full-Custom 1 Kb 8T Synchronous SRAM for Wireless Sensor Network in 90nm CMOS Process Technology," TENCON 2018 - 2018 IEEE Region 10 Conference, Jeju, Korea (South), 2018, pp. 2366–2371.
T. Huang, "Low-Leakage 8T SRAM Based on Body Effect and Power Gating Technique," 2025 IEEE 5th International Conference on Electronic Technology, Communication and Information (ICETCI), Changchun, China, 2025, pp. 1519–1523.
T. V. Reddy and B. K. Madavi, "Designing of schmitt trigger-based architecture 8T SRAM of 256 bit cells under 45 NM technology for low power applications," 2017 International Conference on Intelligent Computing and Control (I2C2), Coimbatore, India, 2017, pp. 1–4.
V. Rukkumani, M. Saravanakumar, and K. Srinivasan, "Design and analysis of SRAM cells for power reduction using low power techniques," 2016 IEEE Region 10 Conference (TENCON), Singapore, 2016, pp. 3058–3062.
A. P. Kumar and R. Lorenzo, "Design of 32×32 (1 KB) SRAM array using 10T SRAM cell for portable low power biomedical applications," Analog Integrated Circuits and Signal Processing, vol. 123, art. no. 36, 2025.
A. Das, A. Bhardwaj, A. Gupta, and G. Raj, "Numerical Comparative Analysis of 10T-SRAM Cells with 6T, 7T, 8T, and 9T Using Vertical Nanowire Tunnel FETs," Semiconductors, vol. 59, pp. 427–435, 2025.
J. Sun, H. Guo, G. Li, and H. Jiao, "An Ultra-Low-Voltage Bit-Interleaved Synthesizable 13T SRAM Circuit," IEEE Journal of Solid-State Circuits, vol. 57, no. 11, pp. 3477–3489, Nov. 2022.
B. V. V. Satyanarayana and M. Durga Prakash, "Design and Performance Analysis of Transmission Gate Based 8T SRAM Cell Using Heterojunction Tunnel Transistors (HETTs)," 2018 International Conference on Recent Innovations in Electrical, Electronics & Communication Engineering (ICRIEECE), Bhubaneswar, India, 2018, pp. 1372–1376.
Y. Shrivastava and T. K. Gupta, "Design of High-Speed Low Variation Static Noise Margin Ternary S-RAM Cells," IEEE Transactions on Device and Materials Reliability, vol. 21, no. 1, pp. 102–110, March 2021.
S. Mahanta, S. Prusti, and S. Patnaik, "Design of Ultra Low Power 6T SRAM Cell Using 180 nm CMOS Technology for Access Enhancement," 2022 International Interdisciplinary Conference on Mathematics, Engineering and Science (MESIICON), Durgapur, India, 2022, pp. 1–6.
A. S. Kumar, K. N. Rao, A. Sujith, T. Dhanuja, and M. V. S. Vinay, "Design and Implementation of 1KB SRAM array in 45 nm Technology for Low-Power Applications," 2023 3rd International Conference on Advances in Computing, Communication, Embedded and Secure Systems (ACCESS), Kalady, Ernakulam, India, 2023, pp. 245–250.
M. A. Turi and J. G. Delgado-Frias, "Effective Low Leakage 6T and 8T FinFET SRAMs: Using Cells With Reverse-Biased FinFETs, Near-Threshold Operation, and Power Gating," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 4, pp. 765–769, April 2020.
A. T. Do, S. M. A. Zeinolabedin, and T. T.-H. Kim, "Energy-Efficient Data-Aware SRAM Design Utilizing Column-Based Data Encoding," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 10, pp. 2154–2158, Oct. 2020.
S. Kumar and C. S. Vinitha, "Design and optimization of 6T SRAM cell at different technology nodes using CMOS for Low power and high-speed neural network computation," 2025 International Conference on Electronics, AI and Computing (EAIC), Jalandhar, India, 2025, pp. 1–5.
H. Oh et al., "Energy-Efficient In-Memory Binary Neural Network Accelerator Design Based on 8T2C SRAM Cell," in IEEE Solid-State Circuits Letters, vol. 5, pp. 70–73, 2022.
C.-C. Wang, R. G. B. Sangalang, and I.-T. Tseng, "A Single-Ended Low Power 16-nm FinFET 6T SRAM Design With PDP Reduction Circuit," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 12, pp. 3478–3482, Dec. 2021.
Y.-T. Wu, F. Ding, M.-H. Chiang, J. F. Chen, and T.-J. K. Liu, "Simulation-Based Study of Low Minimum Operating Voltage SRAM With Inserted-Oxide FinFETs and Gate-All-Around Transistors," IEEE Transactions on Electron Devices, vol. 69, no. 4, pp. 1823–1829, April 2022.
A. S. V. S. V. P. D. Kumar, B. S. Suman, C. A. Sarkar, and D. V. Kushwaha, "Stability and Performance Analysis of Low Power 6T SRAM Cell and Memristor Based SRAM Cell using 45NM CMOS Technology," 2018 International Conference on Recent Innovations in Electrical, Electronics & Communication Engineering (ICRIEECE), Bhubaneswar, India, 2018, pp. 2218–2222.
H S. Gopika, O P. Amritha, and E. Resmi, "Performance Comparison of 6T SRAM and Hybrid SRAM-DRAM Architectures for IoT Applications," 2025 6th International Conference on Control, Communication and Computing (ICCC), Thiruvananthapuram, India, 2025, pp. 1–6.
