Design and Performance Analysis of Novel Hybrid Adder
Keywords:
Adder, Carry Lookahead Adder (CLA), Carry Select Adder (CSELA), Hybrid, Kogge Stone Adder (KSA), Ripple Carry Adder (RCA), XST synthesizerAbstract
Historically, simpler adder designs were sufficient for early computing needs, but as technology advanced, the demand for faster and more efficient designs grew. Due to these requirements, hybrid adders came into existence. Most adders in today’s digital world, such as CSA or CLA, comprise many limitations such as high power consumption and more area. The demand for efficient digital circuits in high-performance computing and embedded systems necessitates the design of fast and area-efficient adders. In this work, some adders like KSA, CLA, CSELA, and RCA are designed which have some limitations. A hybrid adder comprising a combination of CLA and RCA is designed and implementation is done. CLA and RCA each offer distinct advantages and limitations—RCA being simple but slow, and CLA being fast but area-intensive. Hybrid adder designs attempt to combine the best features of different adders, but many suffer from increased complexity, power consumption, and diminishing returns regarding speed improvement. The RCA-CLA combinational hybrid adder is designed and implemented along with various hybrid adder combinations (like CSELA_KSA, CSELA_KSA_KSA), and performance analysis in Xilinx ISE 14.2 is performed in parameters like area in LUTs, delay in nanoseconds and power analysis in mW. Different adders are designed, modules using Verilog HDL and functionality is verified, and performance is analyzed and compared.
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