The Design and Micro-Architectural Performance Optimization of Parallel Adder Circuit

Abstract

This study explores the δx optimization of conventional CMOS carry look-ahead adder of 4-bit, incorporating GDI technology to control the doping level of transistors to enhance performance. The layout of traditional carry look ahead thoroughly utilized S-CMOS (static CMOS), which had a relatively high transistor count. Besides, the input impedance was also very high, so its delay was also high. To address this problem of performance and reduce the number of transistors. GDI-based gates were utilized instead of S-CMOS-based gates. The critical finding highlights significant improvements in the carry look-ahead adder with GDI-based XOR and AND gates concerning power dissipation, delay time, and the area occupied by transistors compared to the conventional S-CMOS-based existing design. The findings also indicate that the GDI approach improves digital systems' overall efficiency and scalability and improves CLA circuits' performance. This study can advance high-performance, low-power arithmetic circuit design, with potential uses in digital signal processing, microprocessors, and portable electronics.