Sub-block Selection Criteria for SEQ Hierarchical Flow-based Formal Verification of Advanced Digital Designs
Keywords:
Design under test (DUT), Factory pattern, Formal convergence, Formal verification, Functional verification, Implementation (IMPL), Object oriented programming (OOPs), Register transfer logic (RTL), Return of investment (ROI), Sequential equivalence (SEQ), Sequential equivalence check (SEC), Specification (SPEC), Synopsys SolvNet Plus™, Synopsys VC Formal™ tool, System on chip (SOC), Universal verification methodology (UVM)Abstract
The critical challenge faced by the latest complex chips on the formal verification and simulation/stimulus-driven platforms is the verification sign-off. The success, failure, comprehensiveness, and reachability of the verification goals created and verified by the formal tool determine the formal verification convergence criterion. The capacity to analytically demonstrate the equivalency between two distinct iterations of identical pre-silicon designs is one of the fundamental methods of formal verification. Versions of pre-silicon designs may vary in terms of bug fixes, low power capability, feature additions or deletions, or needs. This formal verification method is offered by the Synopsys VC FormalTM tool through an integrated formal application called the “Sequential Equivalence (SEQ)” App. Further extending our work on the SEQ hierarchical flow-based formal verification, we developed the sub-block selection criteria for any applicable designs. This study outlines the sub-block criteria for deploying the hierarchical flow-based formal SEQ App towards faster convergence.
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