Sleep Logic-based Low Power Circuit Design by Using Modified Gate Diffusion Input Technique

Abstract

There is a growing demand for developing low-power and highly efficient circuits and systems in almost every application. Low-power VLSI circuit design is of great interest in increasing battery lifetime. The current research comprehensively covers various aspects of power-efficient VLSI circuit design techniques. The basics of various high-performance logic circuits have been analyzed and compared with conventional logic design techniques for better understanding. The proposed logic model is a hybrid design considering the advantages of modified gate diffusion logic and sleep logic methods. Because the modified gate diffusion model can be the best way to minimize circuit area with the required output. Sleep logic can be the best design methodology for reducing power dissipation. The proposed circuits are extensively simulated using Cadence software. The results are compared with several models. The proposed model demonstrates competency in terms of power and silicon area.