Journal of VLSI Design and Signal Processing

Two-Way Tracking System for Buses Augmented by Intelligent Sensor and VLSI Technology: A Study

2026-01-29T11:59:47+00:00

Daily commute, especially for students and professionals relying on public transport, often comes with an element of uncertainty. Where is the bus? Will it be on time? Is it safe? These questions, once the source of considerable anxiety, are now being decisively answered by innovative solutions. One such breakthrough is the two-way tracking system for buses, augmented by intelligent sensor technology. This advanced system transcends the limitations of traditional, unidirectional GPS tracking, ushering in an era of unprecedented transparency, safety, and operational efficiency for bus services. Historically, bus tracking systems have been rudimentary at best. Passengers are left guessing, parents of school children worry, and dispatchers operate with limited real-time information. The two-way tracking system, integrated with a suite of sensors, addresses these issues head-on by creating a dynamic communication loop between the bus, a central control system, and – crucially – the end-users (passengers and parents). While basic GPS tracking has been around for some time, the "two-way" aspect, combined with advanced sensor integration, elevates bus management and passenger experience to an entirely new level. The two-way bus tracking system, powered by an intelligent network of sensors run under VLSI technology, is more than just a tracking device. It's a comprehensive information and communication hub that promises to deliver a smarter, safer, and remarkably more efficient public transportation experience for everyone involved. The era of the truly connected bus is here.

Novel Time-Domain Interleaved Multiplier Sharing Architecture for Ultra-High Throughput FFT Processors

2026-01-23T17:19:38+00:00

This paper presents a novel Time-Domain Interleaved Multiplier Sharing (TDIMS) architecture designed to achieve ultra-high throughput in Fast Fourier Transform (FFT) processors while minimizing hardware complexity. The proposed architecture integrates a dynamically reconfigurable radix-4/8 butterfly processing engine with a centralized shared multiplier pool that is time-interleaved across eight parallel data paths. By exploiting temporal and spatial redundancies in twiddle factor computations, TDIMS reduces the number of complex multipliers by up to 35% compared to conventional multipath delay commutator (MDC) designs. The system also employs a predictive twiddle factor addressing scheme to eliminate memory access bottlenecks. Implemented and synthesized and validated on a Xilinx Virtex-7 FPGA, the processor supports mixed-radix operation and achieves a throughput of 128 GS/s at a 2 GHz clock frequency for 1024/2048-point FFTs. Performance evaluations demonstrate a 4.6× improvement in throughput-per-gate efficiency over state-of-the-art designs, along with significant reductions in logic resource utilization and competitive power consumption. The architecture is highly scalable and well-suited for next-generation wireless applications, including 5G NR and optical OFDM systems, where high speed, flexibility, and area efficiency are critical.

The Art of Signal Processing: Markov Model Approach

2026-02-13T04:46:51+00:00

Signal processing serves as an essential backbone across different domains, including communication systems, healthcare applications, and artificial intelligence components. Both Fourier transforms and wavelet analysis have traditionally been applied to signal decomposition tasks while extracting fundamental features from the data. The deterministic methods fail to handle changing or non-stationary signals that evolve over time, especially for data types such as speech, video, or sensor readings. Markov Models have become a superior alternative to overcome this issue. Using the Markov approach leads to exceptional results when working with data sets that demonstrate sequential dependencies together with uncertain elements. This paper explains the application of Markov Models through an examination of Hidden Markov Models (HMMs) that implement probabilistic signal evolution analysis on time-series data. This paper reviews Markov Model fundamentals while exploring their practical use in speech recognition, together with image segmentation applications, including the problems encountered in practical implementation. The paper examines potential improvements that will result from merging deep learning approaches with traditional Markov Models to improve their operational capabilities.

Mecanum Wheel Robot Car Using FlySky Transmitter and ESP32-Cam Module for Real Time Video Monitoring Approach

2026-01-29T11:44:09+00:00

Omnidirectional mobile robots have gained increasing attention due to their superior maneuverability in confined and dynamic environments compared to conventional wheeled platforms. This paper presents the design and implementation of a Mecanum Wheel Robot Car capable of true holonomic motion combined with real-time video monitoring. The proposed system employs four Mecanum wheels arranged in a standard diagonal configuration, enabling motion in all directions—forward, backward, sideways, diagonal, and rotation—without altering the robot’s orientation. Wireless control is achieved with a FlySky FS-i6 transmitter and FS-iA6B receiver, providing low-latency, reliable command transmission. An Arduino UNO processes PWM signals from the receiver and applies kinematic mixing equations to independently control four DC motors via L293D motor driver modules. To enhance remote situational awareness, an ESP32-CAM module is integrated to provide real-time video streaming over Wi-Fi through a web-based interface. The system architecture combines motion control, wireless communication, and embedded vision into a unified platform. Experimental evaluation demonstrates smooth omnidirectional movement, accurate response to control inputs, and stable live video transmission with minimal latency under indoor operating conditions. The developed robot offers a cost-effective, modular, and scalable solution suitable for applications such as surveillance, indoor automation, inspection, and educational research. The results confirm the effectiveness of Mecanum wheel-based holonomic motion and highlight the potential for future extensions toward autonomous navigation and intelligent robotic systems.

Power Optimization in VLSI Design and Testing: A Concise Survey

2026-03-10T11:56:29+00:00

Rapid advancements in semiconductor technology and aggressive CMOS scaling have made power dissipation one of the most critical challenges in contemporary Very Large-Scale Integration (VLSI) design and testing. As transistor dimensions shrink and circuit density increases, both dynamic and leakage power components significantly influence system reliability, performance, thermal stability, and device lifetime. In particular, power consumption during testing has emerged as a serious concern, as test mode operation often induces substantially higher switching activity than normal functional mode, leading to excessive peak and average power dissipation. This survey presents a comprehensive and systematic review of power optimization techniques employed across VLSI design and test domains, with emphasis on their effectiveness, limitations, and trade-offs. The paper begins by examining the fundamental sources of power dissipation in CMOS circuits, categorizing them into dynamic and static (leakage) power components. Dynamic power is primarily associated with switching activity, capacitive charging and discharging, short-circuit currents, and glitches, while leakage power arises from subthreshold conduction, gate oxide leakage, reverse-biased junction leakage, and other nanoscale effects. With continued technology scaling below deep submicron nodes, leakage power has become comparable to, and in some cases dominant over, dynamic power, particularly during standby and test operations. The influence of threshold voltage reduction, temperature rise, and pattern dependency on leakage behaviour is also highlighted. A detailed review of low-power VLSI design methodologies is presented, encompassing both dynamic and static power reduction strategies. Dynamic power optimization techniques such as device scaling, voltage scaling, transistor sizing, transistor reordering, and precomputation are discussed in terms of their impact on switching activity, delay, and overall performance. Static power reduction techniques, including power gating with sleep transistors, forced transistor stacking, sleepy stack, LECTOR, GALEOR, sleepy keeper, and drain gating approaches, are analyzed for their ability to suppress leakage currents during idle or standby modes. The survey emphasizes that while these techniques can achieve significant leakage reduction, they often introduce design overheads in terms of area, delay, and control complexity. In addition to design-time techniques, the paper extensively reviews power-aware testing methodologies, particularly those related to scan-based testing and Built-In Self-Test (BIST) architectures. Techniques such as scan cell reordering, X-filling strategies, test vector compression and ordering, scan architecture modification, scan clock splitting, and switching activity minimization are examined for their role in reducing average and peak test power. Furthermore, low-power BIST techniques utilizing modified Linear Feedback Shift Registers (LFSRs), dual-speed LFSRs, vector filtering, and test data compression are discussed as effective solutions for minimizing transition density while maintaining acceptable fault coverage. The survey underscores that no single technique is sufficient to address the power challenges posed by modern VLSI systems. Instead, an integrated approach that combines design-time power optimization with test-time power-aware strategies is essential to achieve meaningful reductions in overall power dissipation. The paper also highlights emerging research directions, particularly the growing importance of runtime leakage power and test vector dependency in nanoscale technologies. By consolidating a wide range of established and recent techniques, this work serves as a valuable reference for researchers and designers aiming to develop energy-efficient, reliable, and scalable VLSI systems.