FPGA-based Impulsive Adaptive Filter for Audio Noise Suppression

2026-07-13T13:09:50+00:00

Environmental noise significantly affects the quality and intelligibility of audio signals in modern communication, multimedia, and recording systems. Effective noise suppression techniques are therefore essential to ensure reliable audio transmission and improved listening experiences. Adaptive filtering has emerged as a widely used solution for audio denoising due to its ability to adjust filter parameters in response to changing noise environments. However, conventional adaptive filtering algorithms such as Least Mean Squares (LMS) and Recursive Least Squares (RLS) often encounter limitations related to convergence speed, stability, and computational performance. To overcome these challenges, this work presents the design and FPGA-based implementation of an adaptive audio denoising system using the Impulsive-Metric Variable Regularized Least Squares (IM-VRLS) algorithm. The proposed algorithm employs an exponential error-dependent step-size adaptation mechanism together with a Kalman gain-based weight update strategy to improve filtering accuracy and convergence behavior. The system is implemented on an FPGA platform to evaluate its real-time processing capability and hardware efficiency. Performance is analyzed using Signal-to-Noise Ratio (SNR), Mean Squared Error (MSE), and convergence rate metrics. Experimental results demonstrate that the IM-VRLS algorithm provides superior noise suppression, lower estimation error, and faster convergence compared with conventional LMS and RLS algorithms. Real-time audio streaming through line-in and line-out interfaces further validates the practical applicability of the proposed design. The successful FPGA implementation confirms that the proposed IM-VRLS-based adaptive filter is an efficient and reliable solution for real-time audio denoising applications.

Hybrid Graph Signal Processing and Deep Learning Framework for VLSI Placement Optimization

2026-06-22T08:25:17+00:00

The increasing complexity of Very Large-Scale Integration (VLSI) circuits has intensified the need for efficient placement optimization algorithms capable of handling millions of interconnected components. Traditional placement methods often suffer from excessive computational complexity and longer convergence times when applied to modern nanoscale integrated circuits. This research proposes a Graph Signal Processing (GSP)-based acceleration framework for VLSI placement optimization that leverages spectral graph representations and graph filtering techniques to improve placement efficiency and reduce runtime overhead. The proposed methodology models the placement netlist as a weighted graph, where cells are represented as vertices and interconnections as edges. Graph spectral decomposition is employed to extract low-frequency structural information, enabling accelerated placement refinement and congestion minimization. Experimental evaluation demonstrates that the proposed approach achieves significant improvements in wirelength reduction, placement convergence speed, and computational efficiency compared to conventional analytical placers. Results indicate an average reduction of 18.6% in placement runtime and 11.3% improvement in Half-Perimeter Wire Length (HPWL), while maintaining routing feasibility and timing constraints. The proposed framework provides a scalable and efficient solution for next-generation VLSI physical design automation.

Journal of VLSI Design and Signal Processing

FPGA-based Impulsive Adaptive Filter for Audio Noise Suppression

Hybrid Graph Signal Processing and Deep Learning Framework for VLSI Placement Optimization