https://matjournals.net/engineering/index.php/JOVDSP/issue/feed Journal of VLSI Design and Signal Processing 2026-10-03T09:14:34+00:00 Open Journal Systems <p><strong>JOVDSP</strong> is a peer reviewed journal in the discipline of Computer Science published by the MAT Journals Pvt. Ltd. It is a print and e-journal focused towards the rapid publication of fundamental research papers on all areas of VLSI Design and Signal Processing. VLSI Digital Signal Processing Systems-a unique, comprehensive guide to performance optimization techniques in VLSI signal processing.</p> https://matjournals.net/engineering/index.php/JOVDSP/article/view/4210 Hardware Trojan Detection in FPGA Using PUF-Based Authentication 2026-10-03T09:08:23+00:00 V. Jeyalakshmi jpjeya@annauniv.edu Varalakshmi P jpjeya@annauniv.edu Mohammed Siddique A jpjeya@annauniv.edu <p><em>Hardware Trojans (HTs) are a major threat to the security of a system due to the proliferation of the supply chain of integrated circuits. This study introduces a new detection system based on a 256-bit Physically Unclonable Function (PUF) combined with a SHA-256 hash to authenticate hardware. This scheme makes use of both device identification and design verification to offer a comprehensive solution for device cloning, IP tampering, and unauthorized structural changes. In this regard, the PUF utilizes the physical variation of the semiconductor devices caused by the manufacturing process to produce a unique response. The suggested system uses device-specific identity (PUF response) and design-specific integrity measures (resource utilization) to create an authentication tag. Any malicious intervention, e.g., the insertion of a hardware Trojan, changes the utilization of the resources and produces a hash mismatch, which can be easily detected as a Trojan. Firstly, the PUF-based identification will check for the uniqueness of the hardware device as well as its authenticity, offering protection against any kind of device cloning. Secondly, the SHA-256-based integrity check protects against tampering with the hardware design structure. Therefore, the proposed method can be considered a lightweight, efficient, and scalable solution for enhancing the security of hardware components along the entire IC lifecycle. Moreover, the above-mentioned system can be applied to security-sensitive scenarios such as FPGA architectures, System-on-Chip platforms, cryptographic processors, and Hardware Security Modules. The system is effective on Xilinx Zynq-7020 in both IP tampering and device cloning detection with a very low hardware overhead.</em></p> 2026-10-03T00:00:00+00:00 Copyright (c) 2026 Journal of VLSI Design and Signal Processing