Journal of VLSI Design and Signal Processing

Camera-based Gesture Control of a Robotic Arm using Real-time Hand Tracking

N V Shrihari, Kuldeep G N, Manikant S V, Srushti S B, Narayan Badiger — Tue, 11 Aug 2026 00:00:00 +0000

Human–robot interaction has become an essential area of research in industrial automation, healthcare, assistive technology, and smart manufacturing. This paper presents a camera-based gesture control system for a robotic arm using real-time hand tracking, providing an intuitive and contactless alternative to conventional control interfaces such as joysticks, gloves, and remote controllers. The proposed system utilizes a standard RGB camera to capture live video of hand movements, while computer vision techniques and real-time hand landmark detection are employed to recognize predefined gestures accurately. The detected hand gestures are processed using OpenCV and MediaPipe-based algorithms, which extract finger positions and hand orientation to generate corresponding motion commands for the robotic arm. These commands are transmitted to a microcontroller that actuates servo motors, enabling precise movement of the robotic arm and gripper operations such as opening, closing, lifting, and object manipulation. The markerless approach eliminates the need for wearable sensors or specialized hardware, thereby reducing system cost, improving user comfort, and simplifying deployment. Experimental evaluation demonstrates reliable gesture recognition with low processing latency, allowing smooth and responsive robotic arm operation under normal lighting conditions. The proposed system exhibits high accuracy, ease of implementation, scalability, and adaptability to various robotic platforms. It offers significant potential for applications in industrial automation, remote object handling, healthcare assistance, rehabilitation, education, hazardous environment operations, and smart human–machine interaction. Future enhancements may include deep learning-based dynamic gesture recognition, three-dimensional hand pose estimation, integration with Internet of Things (IoT) platforms, cloud robotics, and augmented reality interfaces to further improve system intelligence, robustness, and operational flexibility.

FPGA-based Impulsive Adaptive Filter for Audio Noise Suppression

S. Raksha, S. Ewins Pon Pushpa — Mon, 13 Jul 2026 00:00:00 +0000

Environmental noise significantly affects the quality and intelligibility of audio signals in modern communication, multimedia, and recording systems. Effective noise suppression techniques are therefore essential to ensure reliable audio transmission and improved listening experiences. Adaptive filtering has emerged as a widely used solution for audio denoising due to its ability to adjust filter parameters in response to changing noise environments. However, conventional adaptive filtering algorithms such as Least Mean Squares (LMS) and Recursive Least Squares (RLS) often encounter limitations related to convergence speed, stability, and computational performance. To overcome these challenges, this work presents the design and FPGA-based implementation of an adaptive audio denoising system using the Impulsive-Metric Variable Regularized Least Squares (IM-VRLS) algorithm. The proposed algorithm employs an exponential error-dependent step-size adaptation mechanism together with a Kalman gain-based weight update strategy to improve filtering accuracy and convergence behavior. The system is implemented on an FPGA platform to evaluate its real-time processing capability and hardware efficiency. Performance is analyzed using Signal-to-Noise Ratio (SNR), Mean Squared Error (MSE), and convergence rate metrics. Experimental results demonstrate that the IM-VRLS algorithm provides superior noise suppression, lower estimation error, and faster convergence compared with conventional LMS and RLS algorithms. Real-time audio streaming through line-in and line-out interfaces further validates the practical applicability of the proposed design. The successful FPGA implementation confirms that the proposed IM-VRLS-based adaptive filter is an efficient and reliable solution for real-time audio denoising applications.

A Scalable and Area Efficient 256, 512 and 1024-Point Pipelined MDC FFT Architectures for OFDM Applications

M Srinivasa Rao, G. L. Madhumati, M. Sailaja — Wed, 12 Aug 2026 00:00:00 +0000

This work presents scalable and area-efficient FFT architectures based on a reusable 64-point radix- multi-path delay commutator (MDC) pipeline FFT. Larger FFT sizes, like 256-, 512-, and 1024-point FFTs, are developed hierarchically by combining preprocessing stages with the adapted 64 base FFT module. As the 64 base FFT architecture employs constant multiplier optimization, it helps to limit the number of complex multipliers to only three for 256-point and four for 512,1024 FFT respectively, significantly reducing arithmetic resource requirements. The proposed design is implemented on a Xilinx Artix-7 FPGA and evaluated in terms of hardware utilization. Experimental results show that the 256-point FFT requires 9391 slice LUTs and 1246 registers, the 512-point FFT uses about 10426 slice LUTs and 1563 registers, and the 1024-point FFT utilizes about 12283 slice LUTs and 1880 registers. Notably, all the proposed implementations avoid dedicated DSP block usage through constant multiplier techniques, leading to improved area efficiency and flexible deployment on resource-constrained FPGA platforms. The proposed approach provides a favourable trade-off between throughput and hardware cost compared with existing FFT architectures, making it well suited for OFDM-based wireless communication and high-performance signal processing applications.

Accelerating IoT Authentication with VLSI-Based Hardware Security

Kazi Kutubuddin Sayyad Liyakat — Fri, 31 Jul 2026 00:00:00 +0000

As the Internet of Things (IoT) proliferates into critical infrastructure, the security of resource-constrained edge devices has become a primary bottleneck. Traditional software-based encryption often incurs prohibitive latency and power overhead, rendering it unsuitable for real-time, low-power applications. This paper explores the paradigm shift toward hardware-intrinsic security by proposing a VLSI-based robust access control mechanism called the DL Security Approach. By integrating Physically Unclonable Functions (PUFs) and hardware-based Trust Zones directly into the silicon architecture, they establish a "Root of Trust" that operates beneath the firmware layer. The proposed design implements a lightweight, high-throughput authentication engine utilizing area-efficient cryptographic primitives. Experimental synthesis results demonstrate that this VLSI implementation achieves a 40% reduction in power consumption and a 60% improvement in authentication speed compared to conventional software-defined access control. This research validates that embedding security primitives at the hardware level is not merely an optimization, but a necessary evolution to ensure the integrity and resilience of the distributed IoT ecosystem.

Hybrid Graph Signal Processing and Deep Learning Framework for VLSI Placement Optimization

Md. Ali — Mon, 22 Jun 2026 00:00:00 +0000

The increasing complexity of Very Large-Scale Integration (VLSI) circuits has intensified the need for efficient placement optimization algorithms capable of handling millions of interconnected components. Traditional placement methods often suffer from excessive computational complexity and longer convergence times when applied to modern nanoscale integrated circuits. This research proposes a Graph Signal Processing (GSP)-based acceleration framework for VLSI placement optimization that leverages spectral graph representations and graph filtering techniques to improve placement efficiency and reduce runtime overhead. The proposed methodology models the placement netlist as a weighted graph, where cells are represented as vertices and interconnections as edges. Graph spectral decomposition is employed to extract low-frequency structural information, enabling accelerated placement refinement and congestion minimization. Experimental evaluation demonstrates that the proposed approach achieves significant improvements in wirelength reduction, placement convergence speed, and computational efficiency compared to conventional analytical placers. Results indicate an average reduction of 18.6% in placement runtime and 11.3% improvement in Half-Perimeter Wire Length (HPWL), while maintaining routing feasibility and timing constraints. The proposed framework provides a scalable and efficient solution for next-generation VLSI physical design automation.