Journal of VLSI Design and Signal Processing

RC Time Constant Investigation using Arduino and a Simple Circuit-based Approach

A. L. Tidar, V. S. Jadhav, S. A. Wankhede — Tue, 09 Jan 2024 00:00:00 +0000

The RC time constant is a measurement of the rate at which a capacitor charges or discharges in an electrical circuit via a resistor. This property is useful in a wide range of applications, including signal processing, power supply, and so on. The purpose of this study is to analyze the RC time constant using an Arduino as well as a simple circuit-based approach. We utilized an Arduino-based approach to clock the time it takes a capacitor to charge through a resistor and then compared the findings to theoretical expectations. We constructed a basic circuit with a capacitor and a resistor for the simple circuit approach. Examine the charge curve data using voltage and time measurements. This research has shed light on the behaviour of the RC time constant and showed the benefits and drawbacks of different configurations.

Design of 2:1 Multiplexer using 16T and 10T in a CMOS Technology

C. Jayakumar — Fri, 19 Jan 2024 00:00:00 +0000

The implementation and analysis of a 2:1 multiplexer employing 16T and 10T CMOS technology are presented in this paper. A multiplexer is an electronic circuit that merges multiple input lines into a single output line. In essence, it is a combinational circuit with several inputs and only one output. As a VLSI design engineer ultimate aim is to reduce power, area and delay. There are two distinct methods for designing a 2:1 multiplexer employed here. One method employs 16 transistors along with NAND gates, while the second one employs static CMOS technology with only 10 transistors. The 2:1 multiplexer designed with 16T using NAND gate consumes substantial power. However, in contrast, the multiplexer implemented with static CMOS technology using 10T is significantly more power efficient, consuming a much lower power. This can also be useful for high-frequency circuits (encoder). CADENCE software tool is used for the implementation and simulation of a multiplexer using 90nm technology.

Difference Adder Graph Algorithm for Reducing LUT Size

Umamaheswari A, S. Ewins Pon Pushpa — Tue, 13 Feb 2024 00:00:00 +0000

The current study introduces an implementation of the Difference Adder Graph Algorithm (DAGA) using Verilog. DAGA, rooted in graph theory and adder circuits, aims to diminish Look Up Tables (LUTs) and power consumption in Field Programmable Gate Arrays (FPGAs). By reducing the number of LUTs required for a specific functionality, DAGA offers a promising alternative for digital circuit optimization. To evaluate its efficacy, the paper contrasts DAGA with the Multiple Constant Multiplication (MCM) method, which leverages Carry Save Adder (CSA) architecture and exploits signed-digit number representations to minimize LUT usage. Experimental findings reveal DAGA's superiority over MCM in both area and power utilization reduction. Implementation details and results indicate a remarkable 49.29% reduction in LUT count and a corresponding 41.8% decrease in power consumption for digital circuits. These outcomes underscore the effectiveness of DAGA in enhancing FPGA efficiency, highlighting its potential as a valuable tool for digital circuit designers seeking to optimize performance and power utilization.

High-Efficient Dynamic Logic Circuit Design

Thu, 18 Apr 2024 00:00:00 +0000

Dynamic logic circuits have received a lot of interest recently because of their excellent performance and energy economy. The keeper circuit of a dynamic logic circuit plays a critical role in preserving the proper logic state, and its layout can have a substantial impact on overall performance and power consumption. This paper concentrates on the design of highly efficient dynamic logic circuits, including a special emphasis on the keeper circuit. To enhance circuit performance while reducing power consumption, two different models are proposed and examined to achieve the most efficient proposed circuit. By altering the keeper circuit design, this paper tackles the hurdles and possible outcomes in enhancing dynamic logic circuits. Proposed Circuit I take up a smaller area whereas Circuit II performs better in terms of time delay. Although each suggested circuit shines in different performance metrics, they may be employed for speedier operation and reduced power usage. The outcomes of the simulation are generated by utilizing the LTspice simulation tool and Cadence virtuoso layout design tool. Time delay, power consumption, and layout area have been analyzed and compared to validate the usefulness of the proposed model.

Enhancement of Infrared Image Processing by CDR Technique

P. Nirmal Kumar, S. M. Suba — Mon, 22 Apr 2024 00:00:00 +0000

Infrared technology's significant advancements have sparked revolutionary transformations in the scientific, technological, military, industrial, and medical sectors. These advancements have reshaped industries, leading to groundbreaking developments and applications, impacting various fields profoundly and paving the way for innovative solutions and enhanced capabilities across diverse domains. Despite considerable advancements, persistent challenges arise from sensor output response errors due to faulty hardware in infrared sensors and limitations in manufacturing processes. These obstacles hinder progress despite notable strides in technology. These challenges adversely affect the quality of infrared images, necessitating remedial measures. In response, a corrective strategy is proposed, focusing on adjusting the gray-scale dynamic range. This innovative compensation algorithm leverages a technique that enhances image intricacies through gray-level dynamic range compensation. Comparative analysis demonstrates its superior efficacy in image enhancement compared to traditional methods, showcasing its ability to address common issues in infrared imaging effectively. Such advancements significantly contribute to enhancing clarity and reliability in critical domains where precision and accuracy are paramount.