Design of 2:1 Multiplexer using 16T and 10T in a CMOS Technology

Abstract

The implementation and analysis of a 2:1 multiplexer employing 16T and 10T CMOS technology are presented in this paper. A multiplexer is an electronic circuit that merges multiple input lines into a single output line. In essence, it is a combinational circuit with several inputs and only one output. As a VLSI design engineer ultimate aim is to reduce power, area and delay. There are two distinct methods for designing a 2:1 multiplexer employed here. One method employs 16 transistors along with NAND gates, while the second one employs static CMOS technology with only 10 transistors. The 2:1 multiplexer designed with 16T using NAND gate consumes substantial power. However, in contrast, the multiplexer implemented with static CMOS technology using 10T is significantly more power efficient, consuming a much lower power. This can also be useful for high-frequency circuits (encoder). CADENCE software tool is used for the implementation and simulation of a multiplexer using 90nm technology.