A Scalable and Area Efficient 256, 512 and 1024-Point Pipelined MDC FFT Architectures for OFDM Applications
Keywords:
Base-64 FFT architecture, Constant multiplier, Field-programmable gate array (FPGA), Radix-FFT, Scalable MDC architectureAbstract
This work presents scalable and area-efficient FFT architectures based on a reusable 64-point radix- multi-path delay commutator (MDC) pipeline FFT. Larger FFT sizes, like 256-, 512-, and 1024-point FFTs, are developed hierarchically by combining preprocessing stages with the adapted 64 base FFT module. As the 64 base FFT architecture employs constant multiplier optimization, it helps to limit the number of complex multipliers to only three for 256-point and four for 512,1024 FFT respectively, significantly reducing arithmetic resource requirements. The proposed design is implemented on a Xilinx Artix-7 FPGA and evaluated in terms of hardware utilization. Experimental results show that the 256-point FFT requires 9391 slice LUTs and 1246 registers, the 512-point FFT uses about 10426 slice LUTs and 1563 registers, and the 1024-point FFT utilizes about 12283 slice LUTs and 1880 registers. Notably, all the proposed implementations avoid dedicated DSP block usage through constant multiplier techniques, leading to improved area efficiency and flexible deployment on resource-constrained FPGA platforms. The proposed approach provides a favourable trade-off between throughput and hardware cost compared with existing FFT architectures, making it well suited for OFDM-based wireless communication and high-performance signal processing applications.
References
T. Hu et al., “Efficient FPGA implementation of multi-channel pipelined large FFT architectures based on SA-MDF algorithm,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 72, no. 5, pp. 2189–2201, May 2025.
S. Sanjeet, B. D. Sahoo and K. K. Parhi, “Comparison of real-valued FFT architectures for low-throughput applications using FPGA,” 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Lansing, MI, USA, pp. 112–115, 2021.
S. He and M. Torkelson, “A new approach to pipeline FFT processor,” Proceedings of International Conference on Parallel Processing, Honolulu, HI, USA, pp. 766–770, 1996.
M. Garrido, J. Grajal, M. Sanchez, and O. Gustafsson, “Pipelined radix-2^k feedforward FFT architectures,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 1, pp. 23–32, Jan. 2013.
T. Cho and H. Lee, “A high-speed low-complexity modified radix 2^5 FFT processor for high rate WPAN applications,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, pp. 187–191, Jan. 2013.
J. Heo, Y. Jung, S. Lee, and Y. Jung, “FPGA implementation of an efficient FFT processor for FMCW radar signal processing,” Sensors, vol. 21, no. 19, Sept. 2021.
D. Massicotte, M. A. Jaber, C. Neili and M. A. Ouameur, “FPGA implementation for the multiplexed and pipelined building blocks of higher radix-2k FFT,” 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS), San Jose, Costa Rica, pp. 1–4, 2020.
M. S. Rao, G. L. Madhumati, and M. Sailaja, “An area efficient 64 point radix-4^2 MDC FFT architecture for OFDM applications,” Integration, vol. 99, Nov. 2024.
F. Zhao, C. Xiao, Z. Wang, X. Du and B. Dong, “Adaptive hybrid FFT: A novel pipeline and memory-based architecture for radix-2k FFT in large size processing,” 2024 IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA), Kaifeng, China, pp. 1341–1348, 2024.
P. Surya, C. Arunachalaperumal, and S. Dhilipkumar, “Performance estimation of low power and area-efficient parallel pipelined FFT,” Measurement Science Review, vol. 25, no. 3, pp. 134–140, 2025.
