Hybrid Graph Signal Processing and Deep Learning Framework for VLSI Placement Optimization
Keywords:
Computer-Aided design (CAD), Electronic design automation, Graph filtering, Graph signal processing, Netlist optimization, Physical Design, Placement acceleration, Placement optimization, Spectral graph theory, VLSI placement, Wirelength minimizationAbstract
The increasing complexity of Very Large-Scale Integration (VLSI) circuits has intensified the need for efficient placement optimization algorithms capable of handling millions of interconnected components. Traditional placement methods often suffer from excessive computational complexity and longer convergence times when applied to modern nanoscale integrated circuits. This research proposes a Graph Signal Processing (GSP)-based acceleration framework for VLSI placement optimization that leverages spectral graph representations and graph filtering techniques to improve placement efficiency and reduce runtime overhead. The proposed methodology models the placement netlist as a weighted graph, where cells are represented as vertices and interconnections as edges. Graph spectral decomposition is employed to extract low-frequency structural information, enabling accelerated placement refinement and congestion minimization. Experimental evaluation demonstrates that the proposed approach achieves significant improvements in wirelength reduction, placement convergence speed, and computational efficiency compared to conventional analytical placers. Results indicate an average reduction of 18.6% in placement runtime and 11.3% improvement in Half-Perimeter Wire Length (HPWL), while maintaining routing feasibility and timing constraints. The proposed framework provides a scalable and efficient solution for next-generation VLSI physical design automation.
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