High-Efficient Dynamic Logic Circuit Design

Abstract

Dynamic logic circuits have received a lot of interest recently because of their excellent performance and energy economy. The keeper circuit of a dynamic logic circuit plays a critical role in preserving the proper logic state, and its layout can have a substantial impact on overall performance and power consumption. This paper concentrates on the design of highly efficient dynamic logic circuits, including a special emphasis on the keeper circuit. To enhance circuit performance while reducing power consumption, two different models are proposed and examined to achieve the most efficient proposed circuit. By altering the keeper circuit design, this paper tackles the hurdles and possible outcomes in enhancing dynamic logic circuits. Proposed Circuit I take up a smaller area whereas Circuit II performs better in terms of time delay. Although each suggested circuit shines in different performance metrics, they may be employed for speedier operation and reduced power usage. The outcomes of the simulation are generated by utilizing the LTspice simulation tool and Cadence virtuoso layout design tool. Time delay, power consumption, and layout area have been analyzed and compared to validate the usefulness of the proposed model.