Power Optimization in VLSI Design and Testing: A Concise Survey

Abstract

Rapid advancements in semiconductor technology and aggressive CMOS scaling have made power dissipation one of the most critical challenges in contemporary Very Large-Scale Integration (VLSI) design and testing. As transistor dimensions shrink and circuit density increases, both dynamic and leakage power components significantly influence system reliability, performance, thermal stability, and device lifetime. In particular, power consumption during testing has emerged as a serious concern, as test mode operation often induces substantially higher switching activity than normal functional mode, leading to excessive peak and average power dissipation. This survey presents a comprehensive and systematic review of power optimization techniques employed across VLSI design and test domains, with emphasis on their effectiveness, limitations, and trade-offs. The paper begins by examining the fundamental sources of power dissipation in CMOS circuits, categorizing them into dynamic and static (leakage) power components. Dynamic power is primarily associated with switching activity, capacitive charging and discharging, short-circuit currents, and glitches, while leakage power arises from subthreshold conduction, gate oxide leakage, reverse-biased junction leakage, and other nanoscale effects. With continued technology scaling below deep submicron nodes, leakage power has become comparable to, and in some cases dominant over, dynamic power, particularly during standby and test operations. The influence of threshold voltage reduction, temperature rise, and pattern dependency on leakage behaviour is also highlighted. A detailed review of low-power VLSI design methodologies is presented, encompassing both dynamic and static power reduction strategies. Dynamic power optimization techniques such as device scaling, voltage scaling, transistor sizing, transistor reordering, and precomputation are discussed in terms of their impact on switching activity, delay, and overall performance. Static power reduction techniques, including power gating with sleep transistors, forced transistor stacking, sleepy stack, LECTOR, GALEOR, sleepy keeper, and drain gating approaches, are analyzed for their ability to suppress leakage currents during idle or standby modes. The survey emphasizes that while these techniques can achieve significant leakage reduction, they often introduce design overheads in terms of area, delay, and control complexity. In addition to design-time techniques, the paper extensively reviews power-aware testing methodologies, particularly those related to scan-based testing and Built-In Self-Test (BIST) architectures. Techniques such as scan cell reordering, X-filling strategies, test vector compression and ordering, scan architecture modification, scan clock splitting, and switching activity minimization are examined for their role in reducing average and peak test power. Furthermore, low-power BIST techniques utilizing modified Linear Feedback Shift Registers (LFSRs), dual-speed LFSRs, vector filtering, and test data compression are discussed as effective solutions for minimizing transition density while maintaining acceptable fault coverage. The survey underscores that no single technique is sufficient to address the power challenges posed by modern VLSI systems. Instead, an integrated approach that combines design-time power optimization with test-time power-aware strategies is essential to achieve meaningful reductions in overall power dissipation. The paper also highlights emerging research directions, particularly the growing importance of runtime leakage power and test vector dependency in nanoscale technologies. By consolidating a wide range of established and recent techniques, this work serves as a valuable reference for researchers and designers aiming to develop energy-efficient, reliable, and scalable VLSI systems.