Novel Time-Domain Interleaved Multiplier Sharing Architecture for Ultra-High Throughput FFT Processors
Keywords:
Fast Fourier Transform (FFT), high-throughput DSP, multiplier sharing, time-domain interleaving, mixed-radix architecture, OFDM, 5G NR, VLSI design.Abstract
This paper presents a novel Time-Domain Interleaved Multiplier Sharing (TDIMS) architecture designed to achieve ultra-high throughput in Fast Fourier Transform (FFT) processors while minimizing hardware complexity. The proposed architecture integrates a dynamically reconfigurable radix-4/8 butterfly processing engine with a centralized shared multiplier pool that is time-interleaved across eight parallel data paths. By exploiting temporal and spatial redundancies in twiddle factor computations, TDIMS reduces the number of complex multipliers by up to 35% compared to conventional multipath delay commutator (MDC) designs. The system also employs a predictive twiddle factor addressing scheme to eliminate memory access bottlenecks. Implemented and synthesized and validated on a Xilinx Virtex-7 FPGA, the processor supports mixed-radix operation and achieves a throughput of 128 GS/s at a 2 GHz clock frequency for 1024/2048-point FFTs. Performance evaluations demonstrate a 4.6× improvement in throughput-per-gate efficiency over state-of-the-art designs, along with significant reductions in logic resource utilization and competitive power consumption. The architecture is highly scalable and well-suited for next-generation wireless applications, including 5G NR and optical OFDM systems, where high speed, flexibility, and area efficiency are critical.
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