Design and Simulation of Key Blocks for SAR ADC using 90/45nm using CMOS Technology
Keywords:
Bootstrapping techniques, CMOS Technology, Sample-and-hold circuits, SAR ADC, Split-capacitorAbstract
With the growing demand for low-power, high-speed data converters in modern electronic systems, SAR ADCs have become the architecture of choice due to their simplicity and CMOS compatibility. This study investigates recent advancements in SAR ADC building blocks—comparator, DAC, and sample-and-hold circuits—optimized for 45nm and 90nm technologies. Strongarm and telescopic comparators exhibit significant speed improvements, offset, and energy efficiency. Split-capacitor DACs with binary-to-thermometer decoding enhance linearity and performance, while R-2R and PWM-based DACs offer scalable and area-efficient alternatives. For sample-and-hold design, bootstrapping techniques and nested quantized analog methods help mitigate charge injection and enhance signal integrity in low-voltage environments. A complete SAR ADC implementation in 28nm CMOS, utilizing alternate comparators and dither-based offset calibration, achieves a speed of 1.6 GS/s and a FoM of 29 fJ/conversion step. Together, these works provide a robust foundation for designing high-performance SAR ADCs in scaled CMOS nodes.
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