High-Performance 8x8 Dadda Multiplier using CSA
Keywords:
Approximate adders, Carry Save Adders (CSA), Dadda multipliers, Digital circuits, VLSIAbstract
Approximate adders have been considered as a potential alternative for error-tolerant applications, with some accuracy, for gains in other circuit-based metrics such as power, area, and delay. Existing approximate adder designs have shown advantages in improving many of these operational features. Nowadays, low-power applications play an important task in designing VLSI-based digital circuits. They demand to investigate different techniques to reduce power consumption in digital circuits while maintaining computational throughput. Many methods are implemented to reduce the power dissipation. In a multiplier, most contribution of power consumption is due to generation and reduction of partial products. Among multipliers, the Dadda multiplier shows enhanced performance in terms of power, area, and delay than other multipliers. Dadda implementation can minimize the number of adder stages required to perform the summation of partial products. In this paper, the implementation is done such that each partial product is processed through CSA, optimizing the addition of intermediate results. ModelSim, a simulation tool, is utilized to validate the functionality and performance of the 8x8 Dadda multiplier with CSA, ensuring accurate multiplication results and verifying the effectiveness of the chosen design approach.
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