RTL Design of APB Protocol based Memory (1K*32) and Testbench
Keywords:
1K32, APB protocol, Efficiency, Embedded systems, Memory module, RTL design, System-on-chip, TestbenchAbstract
This paper presents the Register Transfer Level (RTL) design of a 1K32 memory module based on the Advanced Peripheral Bus (APB) protocol, aiming to address the escalating demands for performance and efficiency in embedded systems. The RTL design is meticulously crafted for optimal read-and-write operations, emphasizing efficiency, low power consumption, and compliance with APB standards. An exhaustive test bench is developed to validate the module's functionality under diverse scenarios. Simulation results demonstrate the correct implementation of operations and robustness of the memory module, showcasing its viability for integration into System-on-Chip (SoC) environments. This work contributes to a scalable and reliable memory solution, laying the groundwork for high-performance embedded systems.
References
K. Rawat, K. Sahni and S. Pandey, "RTL implementation for AMBA ASB APB protocol at system on chip level," 2015 2nd International Conference on Signal Processing and Integrated Networks (SPIN), Noida, India, 2015, pp. 927-930, doi: https://doi.org/10.1109/SPIN.2015.7095347
K. Rawat, K. Sahni and S. Pandey, "Design of AMBA APB bridge with reset controller for efficient power consumption," 2014 9th International Conference on Industrial and Information Systems (ICIIS), Gwalior, India, 2014, pp. 1-5, doi: https://doi.org/10.1109/ICIINFS.2014.7036558
B. N. Manu and P. Prabhavathi, "Design and implementation of AMBA ASB APB bridge," 2013 International Conference on Fuzzy Theory and Its Applications (iFUZZY), Taipei, Taiwan, 2013, pp. 234-238, doi: https://doi.org/10.1109/iFuzzy.2013.6825442.
P. Jain and S. Rao, "Design and Verification of Advanced Microcontroller Bus Architecture-Advanced Peripheral Bus (AMBA-APB) Protocol," 2021 Third International Conference on Intelligent Communication Technologies and Virtual Mobile Networks (ICICV), Tirunelveli, India, 2021, pp. 462-467, doi: https://doi.org/10.1109/ICICV50876.2021.9388549
D. Krishnegowda, "Developing a Bus Functional Model for APB slave using Universal Verification Methodology," 2021 Second International Conference on Smart Technologies in Computing, Electrical and Electronics (ICSTCEE), Bengaluru, India, 2021, pp. 1-5, doi: https://doi.org/10.1109/ICSTCEE54422.2021.9708572
M. R. Gowda and J. Jamuna, “Fault simulation for design for testability inserted designs,”Indonesian Journal of Electrical Engineering and Computer Science, vol. 29, no. 2, pp. 658–658, Nov. 2022, doi: https://doi.org/10.11591/ijeecs.v29.i2.pp658-668.
R. Madhura and M. J. Shantiprasad, “Implementation of Scan Logic and Pattern Generation for RTL Design,” New Trends in Computational Vision and Bio-inspired Computing, pp. 385–396, 2020, doi: https://doi.org/10.1007/978-3-030-41862-5_37.
Madhura.R and Jamuna S “Optimised DFT Architecture through Scan based Design” Grenze International Journal of Engineering and Technology, Jan. 2023, pp. 1093–1101, Available: https://www.academia.edu/119158250/Optimised_DFT_Architecture_through_Scan_based_Design
R. Madhura, K. H. Krishnappa, R. Manasa, and K. P. Yashaswini, “Slack Time Analysis for APB Timer Using Genus Synthesis Tool,” Lecture notes in networks and systems, pp. 207–217, Jan. 2023, doi: https://doi.org/10.1007/978-981-99-4932-8_20.
M. R, K. H. Krishnappa, S. R, S. G, Y. K. P, and S. G. R, “UVM Methodology for ARINC 429 Transceiver in Loop Back Mode,” 2023 3rd International Conference on Mobile Networks and Wireless Communications (ICMNWC), pp. 1–7, Dec. 2023, doi: https://doi.org/10.1109/icmnwc60182.2023.10435932.
D. Mahesh, A. Jamadagni K R, and P. U2, “Performance Analysis of Digital Filters for Wireless Communication System,” Journal of VLSI Design and Signal Processing (e-ISSN: 2581-8449), vol. 7, no. 1, pp. 26–33, 2021, Available: https://matjournals.co.in/index.php/JOVDSP/article/view/3055
K. H. Krishnappa, M. M. Hiremath, M. R, M. R, and N. Holla K, “Semiconductor Fault Diagnosis Using Deep Learning-Based Domain Adaption,” International Journal of Intelligent Systems and Applications in Engineering, vol. 12, no. 9s, pp. 391–404, Mar. 2023, Available: https://ijisae.org/index.php/IJISAE/article/view/4333
