Design of a Low-Power 4-Bit Dadda Multiplier Using Majority Gate Logic for Next-Generation VLSI Systems
Keywords:
Dadda multiplier, Full adder, High-speed digital circuits, Majority gate, MicrowindAbstract
This paper proposes an optimized 4-bit Dadda multiplier architecture that integrates majority gate logic to achieve enhanced power efficiency and computational speed. By utilizing majority logic in the construction of core components such as full adders and half adders, the design effectively minimizes transistor count while preserving operational reliability. Simulation results based on 7nm CMOS technology reveal outstanding performance, achieving a propagation delay of just 8 picoseconds and an exceptionally low power consumption of 3.349 nanowatts. These outcomes underscore the effectiveness of majority gate logic in advancing digital circuit efficiency, offering a compact, scalable, and energy-conscious solution. The proposed design is particularly well-suited for low-power, high-speed VLSI applications, including digital signal processing and machine learning accelerators. By reducing design complexity and power overhead without compromising performance, this work highlights the strong potential of majority gate-based architectures in the development of next-generation integrated circuits, making them highly attractive for modern computing and embedded systems that demand optimized energy usage and rapid processing capabilities.
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