Design and Optimization of a Monotonic Asynchronous Two-Bit Full Adder Using Majority Gate Logic for Low-Power Digital Systems
Keywords:
Asynchronous adder, CMOS, Microwind, Majority gate, Two-bit Full Adder (TFA)Abstract
This paper introduces the design and implementation of a monotonic asynchronous Two-Bit Full Adder (TFA) using majority gate logic, optimized for low-power and high-speed digital systems. Unlike traditional synchronous circuits, the proposed design eliminates the need for a global clock, offering enhanced resilience to process, voltage, and temperature variations. The TFA, implemented in 7nm CMOS technology and simulated using MicroWind 3.9, leverages majority gate logic to achieve superior performance with reduced power consumption and improved fault tolerance. Simulation results reveal a significant reduction in cycle time and area compared to existing monotonic designs, while power consumption increases with voltage, ranging from 0nW at 0.30V to 524.91mW at 5V. The gate dimensions of 8.7μm width and 5.2μm length contribute to a compact design with a total surface area of 45.2μm². Despite higher power consumption at higher voltages, the design maintains its efficiency at low voltages, making it suitable for low-power applications. These results highlight the potential of majority gate logic in delivering compact, power-efficient, and high-performance asynchronous circuits for advanced digital systems.
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