Efficient, Accurate, and Approximate Multiplier Designs for FPGA-Based Hardware Accelerators
Keywords:
Approximate and accurate multipliers, Baugh-Wooley multiplier, Booth multiplier, FPGA, Modified Booth recording, Signed and unsigned multipliersAbstract
High-speed area-efficient multiplier units are used in accelerators. In this project, we propose a multiplier circuit using a radix-8 modified booth algorithm. The radix-8 modified booth algorithm is a technique used for binary multiplication, particularly in hardware implementations like Digital Signal Processors (DSPs) or accelerators. It builds upon the booth algorithm and utilizes groups of three bits instead of two, which effectively reduces the number of partial products involved in the multiplication. The proposed multiplier has a single architecture for both accurate and approximate multiplications and thus leads to a reduction in parameters compared to Baugh-Wooley’s multiplication algorithm, which has a separate architecture for accurate and approximate multipliers. The proposed multiplier’s performance is tested for signed and unsigned multiplications, and also with approximate and accurate conditions. The performance of the proposed multiplier is measured in terms of delay, area, and power. The area of the proposed method is approximately 50% less when compared to Baugh-Wooley’s multiplication for the signed and unsigned multiplications. The delay of the proposed multiplier is 4.62ns less in the case of an accurate and 7.1ns less in the case of an approximate Baugh-Wooley multiplier. And also, the on-chip power of the proposed multiplier circuit is reduced by 36.112 W and 33.73 W when compared to the accurate and approximate Baugh-Wooley multiplier, respectively.
References
G. Zervakis, K. Tsoumanis, S. Xydis, D. Soudris, and K. Pekmestzi, “Design-efficient approximate multiplication circuits through partial product perforation,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 10, pp. 3105-3117, Oct. 2016, doi: //doi.org/10.1109/TVLSI.2016.2535398
H. Jiang, C. Liu, L. Liu, F. Lombardi, and J. Han, “A review, classification, and comparative evaluation of approximate arithmetic circuits,” ACM Journal on Emerging Technologies in Computing Systems, vol. 13, no. 4, pp. 1–34, Aug. 2017, doi: https://doi.org/10.1145/3094124
A. A. Khatibzadeh, K. Raahemifar, and M. Ahmadi, “A 1.8 V 1.1 GHz novel digital multiplier,” Canadian Conference on Electrical and Computer Engineering, 2005., Saskatoon, SK, Canada, 2005, pp. 686-689, doi: https://doi.org/10.1109/CCECE.2005.1557022
S. -R. Kuang, J. -P. Wang and C. -Y. Guo, “Modified booth multipliers with a regular partial product array,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, no. 5, pp. 404-408, May 2009, doi: https://doi.org/10.1109/TCSII.2009.2019334
M.V.S. Ram Prasad. B. Suribabu Naick, Zaamin Zainuddin Aarif, “Design and implementation of high speed 16-bit approximate multiplier” International Journal of Innovative Technology and Exploring Engineering (IJITEE), vol. 8 no. 4, February 2019, Available: https://www.ijitee.org/wp-content/uploads/papers/v8i4/D2808028419.pdf
Li-Rong Wang, Shyh-Jye Jou, and Chung-Len Lee, "A well-structured modified Booth multiplier design," 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, 2008, pp. 85-88, doi: https://doi.org/10.1109/VDAT.2008.4542418
Hwang-Cherng Chow and I-Chyn Wey, "A 3.3 V 1 GHz high speed pipelined Booth multiplier," 2002 IEEE International Symposium on Circuits and Systems (ISCAS), Phoenix-Scottsdale, AZ, USA, 2002, pp. I-I, doi: https://doi.org/10.1109/ISCAS.2002.1009876
M. Kumm, J. Kappauf, M. Istoan, and P. Zipf, “Resource Optimal Design of Large Multipliers for FPGAs,” 2017 IEEE 24th Symposium on Computer Arithmetic (ARITH), London, UK, 2017, pp. 131-138, doi: https://doi.org/10.1109/ARITH.2017.35
Yung-Chih Liang, Ching-Ji Huang, and Wei-Bin Yang, “A 320-MHz 8-bit × 8-bit pipelined multiplier in ultra-low supply voltage,” 2008 IEEE Asian Solid-State Circuits Conference, Fukuoka, Japan, 2008, pp. 73-76, doi: https://doi.org/10.1109/ASSCC.2008.4708732
Sandhya Kanoujia, R. Kumar, and P. Karuppanan, “Low power Radix-4 Booth multiplier design using pass transistor logic,” Lecture notes in electrical engineering, pp. 351–364, Jan. 2023, doi: https://doi.org/10.1007/978-981-99-0973-5_26
C. R. Baugh and B. A. Wooley, “A Two’s complement parallel array multiplication algorithm,” in IEEE Transactions on Computers, vol. C-22, no. 12, pp. 1045-1047, Dec. 1973, doi: https://doi.org/10.1109/T-C.1973.223648
M. D. Ercegovac and T. Lang, “Fast multiplication without carry-propagate addition,” in IEEE Transactions on Computers, vol. 39, no. 11, pp. 1385-1390, Nov. 1990, doi: https://doi.org/10.1109/12.61047
M. Durga Sravanthi, B. Sravya, B. Raghu Vardhan, R. V. Suresh Chandra, and T. Subhashini, “Design of a high-performance approximate Radix-4 Booth multiplier with optimized compressor and encoder for energy-efficient computing”, JoMMR, pp. 23–35, Apr. 2025. Available: https://matjournals.net/engineering/index.php/JoMMR/article/view/1750
C. N. Gopi and T. Sravya, “Speed enhancement of modified Booths encoding algorithm using verilog HDL,” i-manager’s Journal on Digital Signal Processing, vol. 7, no. 1, p. 20, 2019, doi: https://doi.org/10.26634/jdp.7.1.16434
