Design of a High-Performance Approximate Radix-4 Booth Multiplier with Optimized Compressor and Encoder for Energy-Efficient Computing
Keywords:
Approximate computing, Booth multiplier, Digital arithmetic circuits, Energy-efficient hardware, FPGA, low power design, Verilog, Xilinx VivadoAbstract
This paper presents an optimized design of an Approximate Radix-4 Booth Multiplier (ARB4M) that enhances power efficiency, area utilization, and computational delay. The demand for energy-efficient arithmetic units has significantly increased due to the rising adoption of digital signal processing, machine learning accelerators, and other high-performance computing applications. Traditional booth multipliers require extensive hardware resources, making them unsuitable for resource-constrained environments. The proposed ARB4M employs an approximate computing approach that reduces the number of partial products and integrates an optimized compressor design to achieve significant power savings.
Our implementation achieves a dynamic power consumption of 0.079 W, a critical path delay of 10ns, and area utilization of 740 LUTs, 640 FFs, and 200 IOBs. Previous studies have shown that approximate multipliers can achieve up to 40% power savings in error-resilient applications. By leveraging approximate radix-4 encoding, our design improves the power-delay product (PDP) compared to conventional multipliers. The energy per operation is estimated at 192pJ, making it a viable solution for error-tolerant applications such as image processing, low-power embedded systems, and neuromorphic computing. The co-optimization of approximate partial product generation (PPG) and approximate partial product accumulation (PPA) ensures an efficient balance between performance and accuracy, aligning with recent trends in approximate arithmetic circuit design.
Experimental results indicate that the ARB4M achieves a 28% reduction in power consumption while maintaining computational accuracy suitable for DSP and artificial intelligence workloads. Future work includes adapting the architecture for ASIC implementations and exploring dynamic approximation techniques for further optimization. This research demonstrates that approximate computing principles can effectively optimize the power and performance in arithmetic circuits, making them suitable for energy-efficient hardware applications.
References
Mrazek, S. S. Sarwar, L. Sekanina, Z. Vasicek, and K. Roy, “Design of power-efficient approximate multipliers for approximate artificial neural networks,” 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, USA, 2016, pp. 1-7, doi: https://doi.org/10.1145/2966986.2967021
G. Park, J. Kung, and Y. Lee, “Simplified compressor and encoder designs for low-cost Approximate Radix-4 Booth Multiplier,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 3, pp. 1154-1158, March 2023, doi: https://doi.org/10.1109/TCSII.2022.3217696
O. Akbari, M. Kamal, A. Afzali-Kusha and M. Pedram, “Dual-quality 4:2 compressors for utilizing in dynamic accuracy configurable multipliers,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 4, pp. 1352-1361, April 2017, doi: https://doi.org/10.1109/TVLSI.2016.2643003
H. Jiang, J. Han, F. Qiao, and F. Lombardi, “Approximate Radix-8 Booth Multipliers for low-power and high-performance operation,” IEEE Transactions on Computers, vol. 65, no. 8, pp. 2638-2644, 1 Aug. 2016, doi: https://doi.org/10.1109/TC.2015.2493547
V. Leon, G. Zervakis, D. Soudris and K. Pekmestzi, “Approximate hybrid high radix encoding for energy-efficient inexact multipliers,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 3, pp. 421-430, March 2018, doi: https://doi.org/10.1109/TVLSI.2017.2767858
W. Liu, L. Qian, C. Wang, H. Jiang, J. Han, and F. Lombardi, “Design of Approximate Radix-4 Booth Multipliers for error-tolerant computing,” IEEE Transactions on Computers, vol. 66, no. 8, pp. 1435-1441, 1 Aug. 2017, doi: https://doi.org/10.1109/TC.2017.2672976
S. Venkatachalam and S. -B. Ko, “Design of power and area efficient approximate multipliers,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 5, pp. 1782-1786, May 2017, doi: https://doi.org/10.1109/TVLSI.2016.2643639
H. Waris, C. Wang, and W. Liu, “Hybrid low radix encoding-based approximate booth multipliers,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 12, pp. 3367-3371, Dec. 2020, doi: https://doi.org/10.1109/TCSII.2020.2975094
F. Zhu, S. Zhen, X. Yi, H. Pei, B. Hou and Y. He, “Design of Approximate Radix-256 Booth Encoding for error-tolerant computing,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 4, pp. 2286-2290, April 2022, doi: https://doi.org/10.1109/TCSII.2022.3148122
L. Qian, C. Wang, W. Liu, F. Lombardi, and J. Han, “Design and evaluation of an approximate Wallace-Booth multiplier,” 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, Canada, 2016, pp. 1974-1977, doi: https://doi.org/10.1109/ISCAS.2016.7538962
H. Pei, X. Yi, H. Zhou and Y. He, “Design of ultra-low power consumption approximate 4–2 compressors based on the compensation characteristic,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 1, pp. 461-465, Jan. 2021, doi: https://doi.org/10.1109/TCSII.2020.3004929
B. G. Gowda, H. C. Prashanth, V. N. Muralidhara and M. Rao, “Efficient Radix-4 Approximated Modified Booth Multiplier for signal processing and computer vision: A probabilistic design approach,” 2024 25th International Symposium on Quality Electronic Design (ISQED), San Francisco, CA, USA, 2024, pp. 1-8, doi: https://doi.org/10.1109/ISQED60706.2024.10528737
