Journal of Digital Circuitry Innovations in Electrical Devices
https://matjournals.net/engineering/index.php/JDCIED
en-USJournal of Digital Circuitry Innovations in Electrical DevicesDigiCal: Design and Implementation of a Smart Business Calculator for Offline Financial Inclusion of MSMEs
https://matjournals.net/engineering/index.php/JDCIED/article/view/3810
<p><em>Modern smartphone-based Point-of-Sale (POS) systems and digital accounting applications have significantly improved financial transaction management in urban commercial sectors. However, many rural and small-scale MSMEs continue to face challenges due to expensive hardware, unstable internet connectivity, limited digital literacy, and a lack of accessible accounting solutions. Traditional calculators remain affordable and easy to use, but they lack transaction logging, GST computation, analytics, customer due management, or secure record storage. To address these limitations, DigiCal was developed as a smart embedded business calculator specifically designed for offline financial inclusion and digital transformation of MSMEs. </em><em>T</em><em>he proposed system combines the familiarity of a conventional calculator with advanced business functionalities, including automated GST calculation, transaction storage, customer due management, expense tracking, sales analytics, and financial reporting. DigiCal follows an offline-first architecture, using a lightweight SQLite database for secure local storage, while also supporting optional cloud synchronization and web-based analytics when network connectivity becomes available. The hardware implementation is based on a Raspberry Pi Zero 2W integrated with a custom 5×7 matrix keypad, TFT display, rechargeable battery system, speaker feedback module, and lightweight Python software architecture. Experimental evaluation demonstrated reliable real-time transaction processing, stable offline operation, accurate GST computation across multiple tax slabs, responsive user interaction, and efficient local data management. The system also exhibited low power consumption and dependable transaction storage under practical operating conditions. By combining affordability, portability, and ease of use, DigiCal provides a practical alternative to expensive POS systems while preserving the simplicity of traditional calculators. The proposed platform can support improved financial record management, operational efficiency, and sustainable business digitization, thereby contributing to greater financial inclusion for MSMEs operating in low-connectivity environments.</em></p>Atharva GawaliKalpit JareYash NayyarJyoti Botkar
Copyright (c) 2026 Journal of Digital Circuitry Innovations in Electrical Devices
2026-07-022026-07-02221224Design and Implementation of a Scalable Elevator Control System using RTL-to-GDSII ASIC Flow in Cadence
https://matjournals.net/engineering/index.php/JDCIED/article/view/3889
<p><em>Elevator control systems are essential real-time embedded applications that ensure efficient and reliable vertical transportation in modern buildings. This paper presents the design and implementation of a Finite State Machine (FSM)-based elevator controller using Verilog Hardware Description Language (HDL), followed by a complete VLSI design flow from Register Transfer Level (RTL) to GDSII generation. The proposed controller efficiently manages floor requests, travel direction, and door operations through a structured FSM architecture with priority-based request scheduling. Functional verification of the RTL design is performed using Cadence Incisive/Xcelium simulation tools to validate system behavior and state transitions. The verified design is synthesized using Cadence Genus, and Logical Equivalence Checking (LEC) is conducted using Cadence Conformal to ensure consistency between RTL and gate-level implementations. Physical design is carried out using Cadence Innovus, including floorplanning, placement, clock tree synthesis, routing, and timing optimization while satisfying design rule constraints. Static timing analysis using Cadence Tempus verifies setup and hold timing requirements for reliable operation. The finalized layout is generated in GDSII format and visualized through the TinyTapeout GDS viewer, demonstrating a complete chip-ready implementation. Experimental results indicate that the proposed design achieves efficient area utilization, optimized timing performance, and low-power operation. The scalable architecture supports both FPGA and ASIC implementations, making it suitable for modern embedded control applications. This work demonstrates a comprehensive industry-standard RTL-to-GDSII design methodology, effectively bridging digital system design and physical chip realization.</em></p> <p><em> </em></p>M.ThamaraiMonika M.Soorya Vela P.Subiksha L.Swetha R.
Copyright (c) 2026 Journal of Digital Circuitry Innovations in Electrical Devices
2026-07-212026-07-21222540Constant Current Boost Converter for Auxiliary Battery Charging in Electric Vehicles
https://matjournals.net/engineering/index.php/JDCIED/article/view/3803
<p><em>As the world is shifting to EV transportation, the requirement for charging methods that are fast, efficient, and do not wear out batteries too quickly is also rising. Different approaches exist, and each has its own set of trade-offs. Some prioritize speed, others focus on battery health, and a few try to balance both. The proposed system dives into the design and simulation of a lithium-ion battery charging system for electric vehicles. This paper presents the design and simulation of a DC-DC boost converter stepping up the voltage from 12V to 16.8V for a 4.5Ah battery pack. Boost converter parameters, including inductor, capacitor, and switching device, are designed for continuous conduction mode operation at a specified switching frequency. A proportional-integral (PI) controller employing negative feedback control regulates the constant-current-constant-voltage charging by sensing battery current and computing the duty cycle. Simulation is carried out using MATLAB Simulink to observe the ripple voltage spikes across the output voltage by changing the switching frequency. Results show us that 35 KHz provided the least ripple voltage compared to other frequencies on which the system was tested.</em></p>Prathamesh PadamwarAshok SuryawanshiGanesh RahateArnav Bhawat
Copyright (c) 2026 Journal of Digital Circuitry Innovations in Electrical Devices
2026-07-012026-07-0122111