Journal of Digital Circuitry Innovations in Electrical Devices
https://matjournals.net/engineering/index.php/JDCIED
en-USJournal of Digital Circuitry Innovations in Electrical DevicesRole of Graph Neural Networks (GNNs) in Security and Reliability in Circuit Design
https://matjournals.net/engineering/index.php/JDCIED/article/view/4238
<p><em>The relentless scaling of Integrated Circuit (IC) complexity, coupled with a globalized and disaggregated semiconductor supply chain, has intensified concerns surrounding hardware trust, intellectual property protection, and long-term circuit reliability. Traditional verification and reliability-analysis techniques increasingly struggle to keep pace with billion-transistor designs, motivating the adoption of data-driven methods. Because netlists, register-transfer-level descriptions, and physical layouts are naturally expressed as graphs, Graph Neural Networks (GNNs) have emerged as a well-suited machine-learning paradigm for hardware-centric tasks. This article surveys the role of GNNs across two intertwined domains of circuit engineering: hardware security, including hardware Trojan detection, intellectual-property piracy identification, and logic-locking analysis; and circuit reliability, including aging-, process-variation-, and defect-aware performance prediction. The article organizes existing approaches into a coherent taxonomy and compares representative architectures and benchmarks to highlight their capabilities and applications. Open challenges, including scalability to industrial designs, interpretability, adversarial robustness, and integration into commercial electronic design automation flows, are also discussed. The review is intended to orient researchers and practitioners toward promising directions for building trustworthy and dependable next-generation integrated circuits.</em></p> <p><strong> </strong></p>Manas Kumar YogiManam Siva SaiKoppineedi Pushpavalli
Copyright (c) 2026 Journal of Digital Circuitry Innovations in Electrical Devices
2026-10-062026-10-06231626Design of an Energy-Efficient RISC-V Processor for IoT Edge Devices
https://matjournals.net/engineering/index.php/JDCIED/article/view/4262
<p><em>The rapid expansion of Internet of Things (IoT) and edge-computing applications has increased the demand for compact processors capable of providing adequate computational performance under stringent power, area, and memory constraints. Conventional embedded processors frequently require a trade-off between processing throughput and energy consumption, particularly when continuously operating sensor nodes are powered by batteries or energy-limited sources. This research presents the design and performance evaluation of an energy-efficient 32-bit RISC-V processor architecture intended for IoT edge devices. The proposed architecture is based on the RV32I instruction set and incorporates a five-stage pipeline, clock-gating mechanism, optimized arithmetic logic unit, compact register file, and lightweight control architecture. A parameterized simulation dataset containing 1,200 processor configurations is considered by varying clock frequency, pipeline depth, memory size, clock-gating ratio, supply voltage, and arithmetic-unit architecture. Machine-learning models consisting of Random Forest, Support Vector Regression, Artificial Neural Network, and XGBoost are used to predict power consumption, execution time, and area. An optimization framework is subsequently employed to identify a processor configuration providing a suitable balance between power, performance, and hardware area. Illustrative simulation results indicate that the XGBoost model provides the highest prediction accuracy, with R² values of 0.96, 0.95, and 0.94 for power, execution time, and area, respectively. The optimized configuration is estimated to operate at 100 MHz with a power consumption of 38.6 mW, area of 0.91 mm², and average CPI of 1.18. These numerical values are illustrative simulated results intended to demonstrate the proposed methodology and must be replaced with actual RTL, FPGA, or ASIC implementation results before publication.</em></p>Shweta ZambareShivani ShendagePratiksha SurveNilophar ShaikhVaibhav Godase
Copyright (c) 2026 Journal of Digital Circuitry Innovations in Electrical Devices
2026-10-082026-10-08232742Design and Simulation of an Intelligent Solar-Powered EV Charging System with Integrated Energy Management
https://matjournals.net/engineering/index.php/JDCIED/article/view/4108
<p><em>The rapid adoption of Electric Vehicles (EVs) is increasing the need for charging infrastructure that is reliable, efficient, and environmentally sustainable. Conventional charging stations generally depend on grid electricity and can increase local demand during charging periods. India has substantial solar-energy potential, making Photovoltaic (PV)-assisted EV charging a promising approach for reducing grid dependence and increasing renewable-energy utilization. This review examines an intelligent charging architecture integrating a PV array, Maximum Power Point Tracking (MPPT), DC-DC converters, controlled EV battery charging, Wireless Power Transfer (WPT), Internet of Things (IoT) monitoring, and an Energy-Management System (EMS). The reviewed converter structure uses a PV-side boost stage to regulate the operating point near the maximum power point and a downstream buck stage to control battery charging voltage and current. P&O and incremental-conductance MPPT methods are compared with intelligent approaches, while PI/PID control is considered for closed-loop regulation. WPT is reviewed as a cable-free charging interface, with attention to alignment, coupling, efficiency, and standardization. The EMS coordinates available PV power, EV charging demand, optional stationary storage, and grid support. The review identifies a need for integrated simulation studies that evaluate all subsystems under changing irradiation, temperature, battery state of charge, and charging demand. The resulting framework provides a technically consistent basis for MATLAB/Simulink modelling and subsequent experimental validation of solar-powered intelligent EV charging for Indian operating conditions. The proposed system emphasizes coordinated control of renewable generation and EV charging rather than relying solely on conventional grid-based charging. The energy management strategy is designed to prioritize the utilization of available solar power while maintaining suitable battery charging conditions. The system performance is assessed through key parameters such as PV power, DC-link voltage, battery voltage, charging current, battery State of Charge (SOC), and energy flow under different operating conditions. The simulation results are intended to demonstrate the effectiveness of the integrated MPPT, converter control, battery charging, monitoring, and energy-management functions. The study also highlights the potential of intelligent solar-powered charging systems to improve renewable-energy utilization, charging efficiency, and operational flexibility for future EV charging infrastructure.</em></p>Rajlaxmi R. SuryawanshiSatyam S. Chandankar
Copyright (c) 2026 Journal of Digital Circuitry Innovations in Electrical Devices
2026-09-112026-09-1123115