Efficient FIR Filter Design Employing Vedic Multiplier and Carry Lookahead Adder for DSP Applications
Keywords:
Digital signal processing, FIR filter, Lookup table (LUT), Urdhva Tiryakbhyam Sutra, Verilog HDLAbstract
The increasing demand for high-performance, low-power digital signal processing (DSP) systems necessitates efficient arithmetic architectures, particularly for Finite Impulse Response (FIR) filters, where multipliers and adders dominate hardware cost. Existing FIR designs employing Weinberger adders, composite adders, and Weinberger-based multipliers achieve improved performance; however, their complex carry-generation structures and multi-stage adder trees result in elevated lookup-table (LUT) utilisation and increased dynamic power. This paper presents an efficient FIR filter architecture in which each multiply–accumulate operation is realised using an 8×8 Vedic multiplier based on the Urdhva Tiryagbhyam sutra, followed by a Carry Lookahead Adder (CLA) for accumulation. The Vedic multiplier generates partial products in parallel, thereby accelerating multiplication, while the CLA reduces carry-propagation delay through its parallel propagate–generate prefix structure, replacing the composite adder tree of the baseline design. The proposed architecture is implemented in Verilog HDL and verified using the Xilinx Vivado Design Suite. Post-implementation results demonstrate a reduction in LUT utilisation from 93 to 86 and a reduction in dynamic power from 16.186 mW to 15.912 mW relative to the existing Weinberger-based design, confirming its suitability for low-power, high-speed DSP applications.
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