Advance Research in Analog and Digital Communications

Voltage-controlled Oscillators in Phase-locked Loops: Recent Advances and Design Considerations

2026-02-12T10:20:20+00:00

Voltage-Controlled Oscillators (VCOs) constitute a fundamental component in Phase-Locked Loops (PLLs), exerting direct influence on frequency precision, phase noise, power dissipation, and overall system resilience. In the context of the rapid advancement of wireless communication standards, high-speed serial links, and low-power System-on-Chip (SoC) designs, Voltage-Controlled Oscillators (VCOs) have experienced substantial improvements in recent years. VCOs are essential components in PLLs, which are pivotal in diverse applications, including wireless communications, clock generation, and data recovery systems. This paper delves into the latest developments in VCO design, highlighting innovations that improve phase noise, tuning range, linearity, power efficiency, and integration in modern CMOS technologies. Various VCO architectures, such as ring, LC-tank, and hybrid designs, are reviewed with an emphasis on their suitability for low-power and high-frequency applications. Furthermore, key design trade-offs and considerations, including noise sources, frequency stability, and layout techniques, are discussed in the context of PLL system-level requirements. The survey further examines emerging VCO design paradigms, including Digitally Controlled Oscillators (DCOs), adaptive calibration techniques, and machine learning-assisted optimization methodologies. This survey aims to guide designers toward selecting and implementing VCOs that meet stringent performance metrics in next-generation PLL-based systems.

Resilient Distributed Control of HVDC-FACTS Systems under Cyber-attacks and Communication Delays

2026-03-12T08:23:50+00:00

The increasing integration of High Voltage Direct Current (HVDC) links and Flexible AC Transmission System (FACTS) devices in modern power grids has significantly enhanced system flexibility, controllability, and operational efficiency. However, the reliance of these systems on wide-area communication networks exposes them to cyber-attacks and communication delays, posing serious threats to grid stability and reliability. This paper investigates the problem of resilient distributed control of HVDC-FACTS systems under cyber-attacks and communication impairments. The research focuses on the modeling and analysis of False Data Injection (FDI) and Denial-of-Service (DoS) attacks targeting measurement and control communication channels, alongside variable and uncertain communication delays. A delay-tolerant and attack-resilient control framework is developed using distributed and decentralized control architectures to mitigate the impact of these adversarial conditions. The proposed control strategies incorporate attack detection and mitigation mechanisms, as well as robustness against time-varying delays, without relying on a fully centralized control structure. Results demonstrate that the proposed resilient distributed control schemes effectively maintain system stability, power flow regulation, and damping performance under coordinated cyber-attacks and communication delays. Compared to conventional centralized controllers, the distributed approach is anticipated to offer improved scalability, reduced vulnerability to single-point failures, and enhanced resilience against DoS attacks. Simulation studies on benchmark multi-terminal HVDC and FACTS-integrated power systems are expected to confirm that the proposed methods significantly reduce performance degradation, limit the propagation of corrupted data, and ensure acceptable dynamic responses even under severe attack scenarios. Overall, this research contributes to the development of secure and resilient control solutions for cyber-physical power systems, providing practical insights into the trade-offs between centralized and decentralized control architectures and advancing the cybersecurity of future HVDC–FACTS-enabled smart grids.

Design and Implementation of a High-Performance 128-Bit Arithmetic Logic Unit Using Carry Look Ahead Adder, Vedic Multiplier, and Radix-2 Restoring Division

2026-03-30T11:24:11+00:00

This paper presents the design, Verilog HDL implementation, and simulation of a high-performance 128-bit Arithmetic Logic Unit (ALU) targeting advanced digital processing applications. The proposed architecture integrates three optimised arithmetic modules—a 128-bit hierarchical Carry Look Ahead (CLA) adder for fast addition and subtraction, a 128×128 Vedic multiplier based on the Urdhva Tiryakbhyam sutra for high-speed parallel multiplication, and a Radix-2 restoring division unit for accurate quotient and remainder computation. The ALU additionally supports six essential bitwise logical operations—AND, OR, XOR, NOT, NAND, and NOR—controlled through a 3-bit opcode-based selection unit. The complete design is modelled in Verilog HDL, simulated, and functionally verified using Xilinx Vivado on the Kintex-7 XC7K70T FPGA platform. Synthesis results indicate 95.04% LUT utilisation, 24.17% DSP48 block usage, and an estimated critical path delay of 30–50 ns. Simulation waveforms confirm the correct operation of all arithmetic and logical functions, including division remainder generation and division-by-zero detection. The proposed design demonstrates significant improvements in computational width, speed, and functional completeness over conventional 32/64-bit ALU architectures employing Ripple Carry Adders.

A Hybrid Cryptographic–Watermarking Framework for Secure Multimedia Transmission in Adversarial Environments

2026-03-30T11:27:13+00:00

The rapid proliferation of digital multimedia content across open networks has precipitated an unprecedented demand for robust mechanisms that simultaneously ensure confidentiality, authenticity, and integrity of transmitted data. This paper presents a novel hybrid cryptographic watermarking framework that synergistically integrates AES-256 symmetric encryption, RSA-2048 public-key infrastructure, and a robust spread-spectrum digital watermarking algorithm to provide multi-layered protection for multimedia content in adversarial environments. The proposed framework employs a dual-phase protection strategy: in the first phase, the host multimedia content is encrypted using AES-256 in Cypher Block Chaining (CBC) mode, ensuring that the raw content remains confidential against eavesdropping attacks. In the second phase, an imperceptible yet robust digital watermark carrying authentication metadata is embedded into the encrypted domain using Discrete Wavelet Transform (DWT) and Singular Value Decomposition (SVD) techniques. The watermark signal is spread across multiple frequency sub-bands to enhance robustness against geometric, signal processing, and compression attacks. Experimental evaluations conducted on standard benchmark datasets, including USC-SIPI and BOWS-2, demonstrate that the proposed scheme achieves a Peak Signal-to-Noise Ratio (PSNR) exceeding 48 dB, a Normalised Correlation (NC) coefficient above 0.99, and a Bit Error Rate (BER) below 0.001 under various attack scenarios, including JPEG compression, Gaussian noise, rotation, and cropping. The framework also demonstrates resilience against known cryptographic attacks, including chosen-plaintext and known-plaintext attacks. The computational overhead remains within acceptable bounds for real-time multimedia streaming applications, making the proposed framework a viable solution for secure multimedia transmission in adversarial network environments.

Automated Residential Access System with Intelligent Gate and Door Control

2026-03-31T08:16:11+00:00

This paper introduces the design and implementation of an Automatic Gate and Door Opening System for a home using the ESP32 microcontroller. The proposed system controls the opening and closing of gates and doors based on object detection, enhancing home security, convenience, and accessibility. An ultrasonic sensor is utilised to detect the presence of a person or vehicle within a predefined range. Upon detection, the ESP32 interprets the sensor data and actuates a servo motor to control the gate or door mechanism. Additionally, an LED bulb is included to indicate system status and operational states. The system is connected to the Blink IoT mobile application, enabling users to monitor and control the gate remotely through a smartphone over a Wi-Fi network. The design supports real-time operation, low power consumption, and reliable performance under typical home conditions. Experimental results confirm accurate detection, quick response time, and smooth mechanical operation. The proposed solution provides a cost-effective, scalable, and user-friendly approach to home automation, showcasing the effectiveness of IoT-based embedded systems in modern smart home environments.