https://matjournals.net/engineering/index.php/ARADC/issue/feedAdvance Research in Analog and Digital Communications2026-06-29T10:25:50+00:00Open Journal Systems<p><strong>ARADC</strong> is a peer-reviewed journal in the field of Telecommunication Engineering published by MAT Journals Pvt. Ltd. ARADC is a print e-journal focused towards the rapid publication of fundamental research papers in all areas of Analog and Digital Communications. This journal involves the basic principles of the physical transfer of data (a digital bit stream or analog signal) over a point-to-point or point-to-multipoint communication channel. The Journal aims to promote high-quality Research, review articles, and case studies mainly focusing on analog signals for the transmission of information, Discrete Digital and Analogue, Delta Modulation, Quantization, Voice and Data Integration, Analogue Processing Circuits, Citizen Band Radio, Amateur Radio, Cellular Communication. This journal involves comprehensive coverage of all the aspects of Analog and Digital Communications.</p>https://matjournals.net/engineering/index.php/ARADC/article/view/3779Efficient FIR Filter Design Employing Vedic Multiplier and Carry Lookahead Adder for DSP Applications2026-06-29T10:14:45+00:00Vemula Uma Maheswariumamaha9515@gmail.comA. Chandra Sureshumamaha9515@gmail.com<p><em>The increasing demand for high-performance, low-power digital signal processing (DSP) systems necessitates efficient arithmetic architectures, particularly for Finite Impulse Response (FIR) filters, where multipliers and adders dominate hardware cost. Existing FIR designs employing Weinberger adders, composite adders, and Weinberger-based multipliers achieve improved performance; however, their complex carry-generation structures and multi-stage adder trees result in elevated lookup-table (LUT) utilisation and increased dynamic power. This paper presents an efficient FIR filter architecture in which each multiply–accumulate operation is realised using an 8×8 Vedic multiplier based on the Urdhva Tiryagbhyam sutra, followed by a Carry Lookahead Adder (CLA) for accumulation. The Vedic multiplier generates partial products in parallel, thereby accelerating multiplication, while the CLA reduces carry-propagation delay through its parallel propagate–generate prefix structure, replacing the composite adder tree of the baseline design. The proposed architecture is implemented in Verilog HDL and verified using the Xilinx Vivado Design Suite. Post-implementation results demonstrate a reduction in LUT utilisation from 93 to 86 and a reduction in dynamic power from 16.186 mW to 15.912 mW relative to the existing Weinberger-based design, confirming its suitability for low-power, high-speed DSP applications.</em></p>2026-06-29T00:00:00+00:00Copyright (c) 2026 Advance Research in Analog and Digital Communicationshttps://matjournals.net/engineering/index.php/ARADC/article/view/3598Real-time Gesture Mimicking Robotic Arm2026-05-22T05:32:41+00:00Vishwajeet Dhumalgadesiddhi43@gmail.comOmkar Gundagadesiddhi43@gmail.comAnupama Dhabewargadesiddhi43@gmail.comSiddhi Gadegadesiddhi43@gmail.comShubhangi M. Handoregadesiddhi43@gmail.com<p><em>Robotic arms play a crucial role in modern automation by performing repetitive tasks with high accuracy and reliability. This work presents the design and development of a real-time gesture mimicking robotic arm using an ESP32 microcontroller. The system operates on a master-slave mechanism in which the motion provided through a control unit is reproduced by the robotic arm in real time, allowing intuitive and easy operation. User input is provided through potentiometers that generate varying analog signals corresponding to different joint movements. These signals are read and processed by the ESP32, which maps them into suitable control commands for the servo motors. A servo driver module is used to generate precise PWM signals, enabling coordinated and smooth movement of the robotic arm joints, such as base, shoulder, elbow, wrist, and gripper. This setup allows the system to perform pick-and-place tasks efficiently. The mechanical structure of the robotic arm is designed using Fusion 360 and fabricated using 3D printing, ensuring accurate dimensions and lightweight construction. The system demonstrates stable and responsive performance with minimal delay. Due to its low cost, simple design, and ease of use, it is suitable for both educational purposes and basic industrial automation. Future improvements can include wireless control, sensor-based feedback, and intelligent decision-making features to enhance overall functionality. </em></p> <p> </p>2026-05-22T00:00:00+00:00Copyright (c) 2026 Advance Research in Analog and Digital Communicationshttps://matjournals.net/engineering/index.php/ARADC/article/view/37803-D Model Generation using Multi-View and Multi-Data2026-06-29T10:25:50+00:00Atharva Mantrimayank2403deshmukh@gmail.comMayank Deshmukhmayank2403deshmukh@gmail.comRiya Khobragademayank2403deshmukh@gmail.comG. N. Gaikawadmayank2403deshmukh@gmail.com<p><em>Generation of accurate three-dimensional (3D) models from satellite and geospatial data is an important task in remote sensing, photogrammetry, and geospatial analysis. Conventional single-view reconstruction techniques often suffer from incomplete terrain representation, limited depth information, and poor visualization quality. To address these challenges, this paper presents a multi-view and multi-data approach for generating realistic and detailed 3D terrain models. The proposed framework integrates Sentinel-1 SAR imagery, Sentinel-2 optical imagery, Digital Elevation Models (DEM), and Bhuvan geospatial datasets to provide complementary information related to terrain elevation, surface texture, and structural features. The key contribution of this work is the integration of multiple freely available datasets with photogrammetric techniques such as Structure-from-Motion (SfM) and Multi-View Stereo (MVS) to achieve improved terrain representation using a cost-effective workflow. The methodology includes data acquisition, preprocessing, feature extraction, feature matching, image registration, depth estimation, dense point cloud generation, surface reconstruction, and texture mapping. SNAP software is used for satellite image preprocessing and terrain correction, while QGIS is employed for geospatial analysis and 3D visualization. The framework was evaluated based on reconstruction completeness, elevation consistency, terrain representation quality, and visualization effectiveness. Experimental results demonstrated successful generation of DEM, DTM, DSM, river network extraction, and interactive 3D terrain models. The generated models are suitable for applications such as urban planning, environmental monitoring, disaster management, and geospatial analysis. Future work will focus on integrating deep learning techniques and higher-resolution datasets to further enhance reconstruction accuracy and automation.</em></p> <p><strong> </strong></p>2026-06-29T00:00:00+00:00Copyright (c) 2026 Advance Research in Analog and Digital Communicationshttps://matjournals.net/engineering/index.php/ARADC/article/view/3714Simulation and Comparative Analysis of Error Detection Techniques in UART Communication Systems2026-06-12T08:17:07+00:00Aditya Jaiswalmadhumathyp.rvitm@rvei.edu.inJ. Chandanamadhumathyp.rvitm@rvei.edu.inMadhumathy P. madhumathyp.rvitm@rvei.edu.inKavitha N.madhumathyp.rvitm@rvei.edu.in<p><em>Reliable data communication is essential in embedded systems, where transmission errors caused by environmental noise can significantly affect data integrity and system performance. This study presents a software-based simulation of Universal Asynchronous Receiver-Transmitter (UART) communication enhanced with three error detection techniques, namely parity checking, checksum verification, and Cyclic Redundancy Check (CRC). To emulate realistic communication disturbances, a probabilistic Bernoulli noise model is employed, introducing random bit errors during data transmission. The proposed framework evaluates the effectiveness of each error detection method under varying noise conditions using key performance metrics, including error detection rate, reliability, and computational overhead. A comparative analysis is conducted to examine the trade-offs between detection accuracy and processing complexity. The results indicate that parity checking offers the lowest computational cost but has limited capability in detecting multiple-bit errors. Checksum-based detection provides improved performance and reliability, making it suitable for moderate-noise environments. Among the evaluated techniques, CRC demonstrates the highest level of robustness, consistently achieving superior error detection rates even under severe noise conditions. The findings highlight the importance of selecting appropriate error detection mechanisms based on system requirements and communication reliability constraints.</em></p>2026-06-12T00:00:00+00:00Copyright (c) 2026 Advance Research in Analog and Digital Communications