Design and Implementation of a High-Performance 128-Bit Arithmetic Logic Unit Using Carry Look Ahead Adder, Vedic Multiplier, and Radix-2 Restoring Division
Keywords:
128-bit ALU, Carry look ahead adder, FPGA, Radix-2 restoring division, Urdhva Tiryakbhyam, Vedic multiplier, Verilog HDL, VLSI, Xilinx VivadoAbstract
This paper presents the design, Verilog HDL implementation, and simulation of a high-performance 128-bit Arithmetic Logic Unit (ALU) targeting advanced digital processing applications. The proposed architecture integrates three optimised arithmetic modules—a 128-bit hierarchical Carry Look Ahead (CLA) adder for fast addition and subtraction, a 128×128 Vedic multiplier based on the Urdhva Tiryakbhyam sutra for high-speed parallel multiplication, and a Radix-2 restoring division unit for accurate quotient and remainder computation. The ALU additionally supports six essential bitwise logical operations—AND, OR, XOR, NOT, NAND, and NOR—controlled through a 3-bit opcode-based selection unit. The complete design is modelled in Verilog HDL, simulated, and functionally verified using Xilinx Vivado on the Kintex-7 XC7K70T FPGA platform. Synthesis results indicate 95.04% LUT utilisation, 24.17% DSP48 block usage, and an estimated critical path delay of 30–50 ns. Simulation waveforms confirm the correct operation of all arithmetic and logical functions, including division remainder generation and division-by-zero detection. The proposed design demonstrates significant improvements in computational width, speed, and functional completeness over conventional 32/64-bit ALU architectures employing Ripple Carry Adders.
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