ASPI Protocol Design in Verilog and Simulation

Abstract

In this project, we present a design of a multi-slave ASPI communication controller intended for integration into system-on-chip platforms and embedded systems. The proposed controller emphasizes reusability, modularity, and robustness, supported by a complete verification methodology that includes RTL simulation, testbench-based validation, and FPGA prototyping. The main objective of this work is to develop a four-wire advanced serial peripheral interface controller for educational and research applications. The design process begins at the micro-architectural level, focusing on RTL development of individual functional units. Each internal block of the ASPI controller is modeled in Verilog HDL and verified independently using dedicated testbenches to ensure correctness before system-level integration. Once functional verification is complete, the ASPI controller is mapped to the memory I/O space and incorporated into an existing RISC32 pipelined CPU designed at UTAR. Following successful integration, the synthesized design is implemented on FPGA hardware. Finally, the controller is interfaced with the serial communication to demonstrate wireless communication. In this setup, the ASPI controller operates as the master device, while the CC2420 transceiver functions as the slave, using the standard four-wire ASPI signals: MOSI, MISO, SCLK, and SS. The expected deliverables include the Verilog HDL source code for the advanced serial peripheral interface controller with test benches, simulation and verification results, FPGA-synthesized hardware design, and a fully integrated FPGA implementation that is tested and analyzed using serial communication.