Design and Optimization of RISC V Processor

Abstract

The RISC-V Instruction Set Architecture (ISA) has recently gained popularity due to its open-source nature, modular design, and flexibility. This paper provides a comprehensive overview of the RISC-V architecture, covering its history, instruction set, and features. Furthermore, the advantages of RISC-V and its potential applications in various industries are discussed. RISC-V follows a load-store architecture, where data processing instructions operate on register values and memory accesses are done using load and store instructions. The ISA includes 32 General-Purpose Registers (GPRs) that are 32-bit wide, along with Special-Purpose Registers (SPRs) for system-level operations. The modular design of RISC-V allows customization for specific applications, with subsets like RV32I, RV64I, and RV128I specifying word size and register count. Optional extensions are M, A, F, and D, providing additional functionality for integer multiplication and division, atomic memory operations, single-precision floating-point, and double-precision floating-point operations. RISC-V is known for its attractive features, making it a preferred choice for processor design.