Design and Analysis of RISC V Processor Architecture

Abstract

This research paper presents the design and analysis of a 32-bit RISC-V processor architecture incorporating a hardwired control unit and employing a five-stage pipelining technique using Verilog. The RISC-V Instruction Set Architecture (ISA) has gained significant attention due to its open standard, simplicity, and modularity, making it an ideal candidate for various computing applications. The proposed architecture utilizes a hardwired control unit to manage instruction execution within the pipeline stages efficiently, enhancing the processor's performance and reducing overhead associated with control logic. The five-stage pipelining approach increases throughput and achieves better instruction-level parallelism. Through extensive simulation and analysis, the performance metrics, including throughput, latency, and resource utilization, are evaluated to validate the effectiveness of the proposed design. Additionally, comparisons are made with alternative control unit architectures and pipelining strategies to demonstrate the advantages of the proposed approach. A hardwired control unit that overcomes the limitation of the delay unit method aims to improve the speed, reduce the number of flip flops, i.e., area, and analyze the minimum clock period, which translates to a maximum operating frequency.