Adaptive Neuromorphic Edge Processors for Real-time Anomaly Detection in IoT Sensor Networks
Keywords:
Few-shot adaptation, Memristor crossbar, Neuromorphic edge processor, Spiking neural networks, Continual learningAbstract
Background: Edge intelligence is constrained by power, data volume, catastrophic forgetting, and limited adaptability. Conventional digital processors cannot sustain always-on continual learning, while neuromorphic systems lack mature on-device adaptation.
Purpose: ANEP introduces a full-stack, memristor-based neuromorphic architecture for ultra-low-power, event-driven continual learning at the sensor edge.
Methods: ANEP integrates a 3D memristor crossbar, sparse event front-end, RISC-V controller, hierarchical memory, adaptive power management, and hardware-aware SNN training. Continual learning employs a four-phase algorithm combining STDP, hardware-friendly surrogate gradients (HASG), selective threshold-based online protection (STOP), elastic weight consolidation, and prioritized experience replay. Device non-idealities are mitigated via noise-aware training, local updates, and resource-triggered execution in 40nm CMOS with BEOL memristors.
Novelty: Unifies sensor-to-spike pipeline, analog in-memory computing, energy-proportional triggering, and hybrid regularization-replay in a compact processor, delivering sub-100 pJ synaptic updates with 95% energy reduction versus full retraining.
Findings: ANEP achieves <10 mW power, 80% data reduction, 4–7 bit precision with <5% mapping loss, >85% few-shot accuracy within 5 examples, 11.1% forgetting (22% relative improvement), and 95–99% adaptation success. Hardware circuits consume 100 pJ/update at 0.05 mm².
Conclusion: ANEP enables autonomous, lifelong edge intelligence, outperforming digital accelerators in power, latency, and adaptability for sparse, event-driven applications.
Recommendation: Prioritize advanced memristor materials, hybrid precision, on-chip calibration, and real-world IoT deployments to address variability and endurance.
References
A. Al-Fuqaha, M. Guibene, N. Mohammadi, M. Aledhari, and M. Ayyash, “Internet of Things: A Survey on Enabling Technologies, Protocols, and Applications,” IEEE Communications Surveys & Tutorials, vol. 17, no. 4, pp. 2347–2376, Fourth Quarter, 2015.
V. Chandola, A. Banerjee, and V. Kumar, “Anomaly detection: A survey,” ACM Computing Surveys, vol. 41, no. 3, pp. 1–58, July 2009.
T. P. Raptis, A. Passarella, and M. Conti, “Data Management in Industry 4.0: State of the Art and Open Challenges,” IEEE Access, vol. 7, pp. 97052–97093, 2019.
K. Stouffer, V. Pillitteri, S. Lightman, M. Abrams, and A. Hahn, Guide to Industrial Control Systems (ICS) Security, NIST Special Publication 800-82 Rev. 2, Gaithersburg, MD, USA: National Institute of Standards and Technology, 2015.
W. Shi, J. Cao, Q. Zhang, Y. Li, and L. Xu, “Edge Computing: Vision and Challenges,” IEEE Internet of Things Journal, vol. 3, no. 5, pp. 637–646, October 2016.
N. D. Lane et al., “DeepX: A Software Accelerator for Low-Power Deep Learning Inference on Mobile Devices,” in Proceedings of the 15th ACM/IEEE International Conference on Information Processing in Sensor Networks (IPSN), Vienna, Austria, April 2016, pp. 1–12.
M. A. Ferrag, L. Maglaras, S. Moschoyiannis, and H. Janicke, “Deep Learning for Cyber Security Intrusion Detection: Approaches, Datasets, and Comparative Study,” Journal of Information Security and Applications, vol. 50, p. 102419, February 2020.
V. Sze, Y.-H. Chen, T.-J. Yang, and J. S. Emer, “Efficient Processing of Deep Neural Networks: A Tutorial and Survey,” Proceedings of the IEEE, vol. 105, no. 12, pp. 2295–2329, December 2017.
G. Indiveri et al., “Neuromorphic silicon neuron circuits,” Frontiers in Neuroscience, vol. 5, p. 73, 2011.
M. Hu, C. E. Graves, C. Li, Y. Li, N. Ge, and R. S. Williams, “Memristor-Based Analog Computation and Neural Network Classification with a Dot Product Engine,” Advanced Materials, vol. 30, no. 9, p. 1705914, 2018.
M. Davies et al., “Advancing Neuromorphic Computing With Loihi: A Survey of Results and Outlook,” Proceedings of the IEEE, vol. 109, no. 5, pp. 911–934, May 2021.
Y. Liu et al., “An 82 nW 0.53 pJ/SOP Clock-Free Spiking Neural Network with 40 µs Latency for AIoT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique,” in Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, February 2022, pp. 372–374.
E. O. Neftci, H. Mostafa, and F. Zenke, “Surrogate Gradient Learning in Spiking Neural Networks: Bringing the Power of Gradient-Based Optimization to Spiking Neural Networks,” IEEE Signal Processing Magazine, vol. 36, no. 6, pp. 51–63, November 2019.
P. Malhotra, A. Ramakrishnan, G. Anand, L. Vig, P. Agarwal, and G. Shroff, “LSTM-based encoder–decoder for multi-sensor anomaly detection,” arXiv preprint, 2016.
F. T. Liu, K. M. Ting, and Z.-H. Zhou, “Isolation forest,” in Proceedings of the 8th IEEE International Conference on Data Mining (ICDM), Pisa, Italy, December 2008, pp. 413–422.
C. Zhou and R. C. Paffenroth, “Anomaly detection with robust deep autoencoders,” in Proceedings of the 23rd ACM SIGKDD International Conference on Knowledge Discovery and Data Mining, Halifax, NS, Canada, August 2017, pp. 665–674.
T. Schlegl, P. Seeböck, S. M. Waldstein, U. Schmidt-Erfurth, and G. Langs, “Unsupervised anomaly detection with generative adversarial networks to guide marker discovery,” in Proceedings of the International Conference on Information Processing in Medical Imaging (IPMI), Boone, NC, USA, June 2017, pp. 146–157.
A. Capotondi et al., “CMix-NN: Mixed low-precision CNN library for memory-constrained edge devices,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 5, pp. 871–875, May 2020.
V. J. Reddi et al., “MLPerf Mobile Inference Benchmark,” arXiv preprint, 2020.
S. I. Venieris and C.-S. Bouganis, “fpgaConvNet: A Framework for Mapping Convolutional Neural Networks on FPGAs,” in Proceedings of the IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Washington, DC, USA, May 2016, pp. 40–47.
W. Maass, “Networks of spiking neurons: The third generation of neural network models,” Neural Networks, vol. 10, no. 9, pp. 1659–1671, 1997.
P. A. Merolla et al., “A million spiking-neuron integrated circuit with a scalable communication network and interface,” Science, vol. 345, no. 6197, pp. 668–673, August 2014.
S. B. Furber, F. Galluppi, S. Temple, and L. A. Plana, “The SpiNNaker Project,” Proceedings of the IEEE, vol. 102, no. 5, pp. 652–665, May 2014.
M. Hu, H. Li, Q. Wu, and G. S. Rose, “Hardware realization of BSB recall function using memristor crossbar arrays,” in Proceedings of the 49th Annual Design Automation Conference (DAC), San Francisco, CA, USA, June 2012, pp. 498–503.
J. Kirkpatrick et al., “Overcoming catastrophic forgetting in neural networks,” Proceedings of the National Academy of Sciences of the United States of America, vol. 114, no. 13, pp. 3521–3526, March 2017.
B. McMahan, E. Moore, D. Ramage, S. Hampson, and B. A. y Arcas, “Communication-efficient learning of deep networks from decentralized data,” in Proceedings of the 20th International Conference on Artificial Intelligence and Statistics (AISTATS), Fort Lauderdale, FL, USA, April 2017, pp. 1273–1282.
S. Ravi and H. Larochelle, “Optimization as a model for few-shot learning,” in Proceedings of the International Conference on Learning Representations (ICLR), Toulon, France, April 2017.
G. Gallego et al., “Event-Based Vision: A Survey,” IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 44, no. 1, pp. 154–180, January 2022.
A. Balaji, F. Corradi, A. Das, S. M. P. Dinakarrao, and F. Catthoor, “A Dynamically Adaptive Approach for Time-Series Forecasting at the Edge,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 7, pp. 1415–1428, July 2021.
S. Yu, “Neuro-inspired computing with emerging nonvolatile memory,” Proceedings of the IEEE, vol. 106, no. 2, pp. 260–285, February 2018.
J. L. Lobo, J. Del Ser, A. Bifet, and N. Kasabov, “Spiking Neural Networks and Online Learning: An Overview and Perspectives,” Neural Networks, vol. 121, pp. 88–100, January 2020.
A. Malinin and M. Gales, “Predictive Uncertainty Estimation via Prior Networks,” in Proceedings of the 32nd International Conference on Neural Information Processing Systems (NeurIPS), Montréal, QC, Canada, December 2018.
Y. Chen, T. Luo, S. Liu, S. Zhang, L. He, and J. Wang, “DaDianNao: A Machine-Learning Supercomputer,” in Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Cambridge, United Kingdom, December 2014, pp. 609–622.
D. Ielmini and H.-S. P. Wong, “In-memory computing with resistive switching devices,” Nature Electronics, vol. 1, no. 6, pp. 333–343, June 2018.
M. A. Lastras-Montaño et al., “Training and Inference of Deep Neural Networks using Non-Ideal Resistive Crossbars,” IEEE Transactions on Electron Devices, vol. 68, no. 6, pp. 2816–2822, June 2021.
A. Ren et al., “SC2: A Secure and Scan-Chain-Enabled CNN Training and Inference Accelerator Using Memristor Crossbar Arrays,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 8, no. 3, pp. 386–398, September 2018.
J. K. Eshraghian et al., “Training Spiking Neural Networks Using Lessons From Deep Learning,” Proceedings of the IEEE, vol. 111, no. 9, pp. 1016–1054, September 2023.
P. Perera, P. Oza, and V. M. Patel, “One-Class Classification: A Survey,” arXiv preprint, 2021.
G. Bellec, D. Salaj, A. Subramoney, R. Legenstein, and W. Maass, “Long short-term memory and Learning-to-learn in networks of spiking neurons,” in Proceedings of the 32nd International Conference on Neural Information Processing Systems (NeurIPS), Montréal, QC, Canada, December 2018.
F. Sattler, S. Wiedemann, K.-R. Müller, and W. Samek, “Robust and Communication-Efficient Federated Learning from Non-IID Data,” IEEE Transactions on Neural Networks and Learning Systems, vol. 31, no. 9, pp. 3400–3413, September 2020.
S. Yu et al., “Memristor-driven neuromorphic computing with crossbar arrays: A hardware perspective,” in Memristor Computing, 2025, pp. 1–25.
X. Zhang et al., “Edge learning using a fully integrated neuro-inspired memristor chip,” Science, vol. 381, no. 6653, pp. 1205–1211, September 2023.
O. Krestinskaya et al., “Neuro-memristive circuits for edge computing: A review,” arXiv preprint, 2018 (updated version).
“Menage: Mixed-Signal Event-Driven Neuromorphic Accelerator for Edge Applications,” arXiv preprint, October 2024.
G. C. Adam et al., “3-D Memristor Crossbars for Analog and Neuromorphic Computing Applications,” IEEE Transactions on Electron Devices, vol. 64, no. 1, pp. 312–318, January 2017.
Y. S. An et al., “Implementation of monolithic 3D integrated TiOₓ memristor-based neural network for high-performance in-memory computing,” Nano Energy, vol. 139, Art. no. 110999, June 2025.
S. Choi et al., “Wafer-scale fabrication of memristive passive crossbar circuits for brain-scale neuromorphic computing,” Nature Communications, vol. 16, Art. no. 63831, 2025.
J. Bae et al., “3-dimensional multistate memristor structures based neuromorphic devices for high-density in-memory computing,” Materials Science in Semiconductor Processing, early access, 2025.
