Design, Simulation, and Analysis of 5:32 Decoder using 90nm and 45nm Technology in Cadence
Keywords:
5:32 decoder design, 90nm CMOS technology, Address decoder optimization, Digital logic design, Low power VLSI circuitsAbstract
This project presents the design, simulation, and analysis of a 5:32 decoder using 90nm and 45nm CMOS technology nodes in the Cadence design environment. The 5:32 decoder is a critical digital component, particularly in memory circuits like SRAM, significantly affecting access time and power consumption. The proposed design utilizes a combination of NAND-NOR alternate stages, pre-decoder circuits, and replica inverter chains to optimize performance. By incorporating pre-decoder logic, the number of gate stages and transistors is reduced, resulting in lower delay and power dissipation compared to traditional and universal block architectures. Simulation results demonstrate that the proposed architecture achieves improved speed and reduced power consumption, with the 45nm technology node offering further enhancements due to its smaller feature size. Comparative analysis across both technology nodes highlights the trade-offs in delay, power, and area, providing valuable insights for future low-power, high-speed VLSI circuit design. All simulations and layout verifications were performed using Cadence tools, confirming the effectiveness and scalability of the proposed 5:32 decoder architecture.
References
M. Madhusudhan Reddy, K. V. Challa and B. Srinivasa Raja, “An energy efficient static address decoder for high-speed memory applications,” 2022 7th International Conference on Communication and Electronics Systems (ICCES), Coimbatore, India, 2022, pp. 50-53, doi: https://doi.org/10.1109/ICCES54183.2022.9835902
C. S. Pittala, M. Lavanya, V. Vijay, Y. V. J. C. Reddy, S. C. Venkateswarlu and R. R. Vallabhuni, “Energy efficient decoder circuit using source biasing technique in CNTFET technology,” 2021 Devices for Integrated Circuit (DevIC), Kalyani, India, 2021, pp. 610-615, doi: https://doi.org/10.1109/DevIC50843.2021.9455824
K. Monga, S. Aggarwal, N. Chaturvedi and S. Gurunarayanan, “A novel decoder design for logic computation in SRAM: CiM-SRAM,” 2021 IEEE 18th India Council International Conference (INDICON), Guwahati, India, 2021, pp. 1-4, doi: https://doi.org/10.1109/INDICON52576.2021.9691664
D. Balobas and N. Konofaos, “Design of low-power high-performance 2–4 and 4–16 mixed-logic line decoders,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 2, pp. 176-180, Feb. 2017, doi: https://doi.org/10.1109/TCSII.2016.2555020
N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed., Boston, MA, USA: Addison-Wesley, 2010.
V. B S and S. B. K C, “Layout design of row decoder using cadence,” International Journal for Research in Applied Science and Engineering Technology, vol. 10, no. 8, pp. 461–468, Aug. 2022, doi: https://doi.org/10.22214/ijraset.2022.46214
Cadence Design Systems Inc., “Virtuoso Analog Design Environment User Guide,” 2020. Available: https://www.cadence.com/
