Design and Simulation of a Reconfigurable Coprocessor in FPGA
Keywords:
Coprocessor, Dynamic, Floating-point arithmetic, FPGA, Partitioning, ReconfigurableAbstract
In designing different hardware, a reconfigurable architecture with dedicated instruction sets allows the coprocessor designed to satisfy the estimation, which can be decomposed into basic common operations. A reconfigurable architecture is a computer architecture that combines some of the flexibility of software with high-performance hardware. It is a dynamic, cost-effective, and power-efficient approach. Furthermore, a memory-reuse strategy in instructions avoids the demand for temporary memory for complex operations. Some of the memory reuse techniques include avoiding redundancy of data, partitioning the memory, optimizing memory allocation, and de-allocation. Finally, performing the matrix operations and special computation using floating-point arithmetic and trigonometric functions can be done. This design is for low hardware resource usage and memory requirements.
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