Design of an Energy-Efficient RISC-V Processor for IoT Edge Devices

Abstract

The rapid expansion of Internet of Things (IoT) and edge-computing applications has increased the demand for compact processors capable of providing adequate computational performance under stringent power, area, and memory constraints. Conventional embedded processors frequently require a trade-off between processing throughput and energy consumption, particularly when continuously operating sensor nodes are powered by batteries or energy-limited sources. This research presents the design and performance evaluation of an energy-efficient 32-bit RISC-V processor architecture intended for IoT edge devices. The proposed architecture is based on the RV32I instruction set and incorporates a five-stage pipeline, clock-gating mechanism, optimized arithmetic logic unit, compact register file, and lightweight control architecture. A parameterized simulation dataset containing 1,200 processor configurations is considered by varying clock frequency, pipeline depth, memory size, clock-gating ratio, supply voltage, and arithmetic-unit architecture. Machine-learning models consisting of Random Forest, Support Vector Regression, Artificial Neural Network, and XGBoost are used to predict power consumption, execution time, and area. An optimization framework is subsequently employed to identify a processor configuration providing a suitable balance between power, performance, and hardware area. Illustrative simulation results indicate that the XGBoost model provides the highest prediction accuracy, with R² values of 0.96, 0.95, and 0.94 for power, execution time, and area, respectively. The optimized configuration is estimated to operate at 100 MHz with a power consumption of 38.6 mW, area of 0.91 mm², and average CPI of 1.18. These numerical values are illustrative simulated results intended to demonstrate the proposed methodology and must be replaced with actual RTL, FPGA, or ASIC implementation results before publication.