Role of Graph Neural Networks (GNNs) in Security and Reliability in Circuit Design
Keywords:
Circuit reliability, Electronic design automation, Graph neural networks, Hardware security, Hardware trojan detection, Logic lockingAbstract
The relentless scaling of Integrated Circuit (IC) complexity, coupled with a globalized and disaggregated semiconductor supply chain, has intensified concerns surrounding hardware trust, intellectual property protection, and long-term circuit reliability. Traditional verification and reliability-analysis techniques increasingly struggle to keep pace with billion-transistor designs, motivating the adoption of data-driven methods. Because netlists, register-transfer-level descriptions, and physical layouts are naturally expressed as graphs, Graph Neural Networks (GNNs) have emerged as a well-suited machine-learning paradigm for hardware-centric tasks. This article surveys the role of GNNs across two intertwined domains of circuit engineering: hardware security, including hardware Trojan detection, intellectual-property piracy identification, and logic-locking analysis; and circuit reliability, including aging-, process-variation-, and defect-aware performance prediction. The article organizes existing approaches into a coherent taxonomy and compares representative architectures and benchmarks to highlight their capabilities and applications. Open challenges, including scalability to industrial designs, interpretability, adversarial robustness, and integration into commercial electronic design automation flows, are also discussed. The review is intended to orient researchers and practitioners toward promising directions for building trustworthy and dependable next-generation integrated circuits.
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