Design and Implementation of a Scalable Elevator Control System using RTL-to-GDSII ASIC Flow in Cadence

Abstract

Elevator control systems are essential real-time embedded applications that ensure efficient and reliable vertical transportation in modern buildings. This paper presents the design and implementation of a Finite State Machine (FSM)-based elevator controller using Verilog Hardware Description Language (HDL), followed by a complete VLSI design flow from Register Transfer Level (RTL) to GDSII generation. The proposed controller efficiently manages floor requests, travel direction, and door operations through a structured FSM architecture with priority-based request scheduling. Functional verification of the RTL design is performed using Cadence Incisive/Xcelium simulation tools to validate system behavior and state transitions. The verified design is synthesized using Cadence Genus, and Logical Equivalence Checking (LEC) is conducted using Cadence Conformal to ensure consistency between RTL and gate-level implementations. Physical design is carried out using Cadence Innovus, including floorplanning, placement, clock tree synthesis, routing, and timing optimization while satisfying design rule constraints. Static timing analysis using Cadence Tempus verifies setup and hold timing requirements for reliable operation. The finalized layout is generated in GDSII format and visualized through the TinyTapeout GDS viewer, demonstrating a complete chip-ready implementation. Experimental results indicate that the proposed design achieves efficient area utilization, optimized timing performance, and low-power operation. The scalable architecture supports both FPGA and ASIC implementations, making it suitable for modern embedded control applications. This work demonstrates a comprehensive industry-standard RTL-to-GDSII design methodology, effectively bridging digital system design and physical chip realization.