Design and Performance Analysis of a 45 nm CMOS BCD Adder using LTSpice Simulation
Keywords:
BCD adder, CMOS VLSI design, Decimal arithmetic units, Low-power digital circuits, 45 nm technologyAbstract
Binary-Coded Decimal (BCD) arithmetic continues to play a vital role in commercial and business calculations, wherever exact number accuracy is non-negotiable. Conventional BCD adders usually follow a two-stage approach—initially performing binary addition, then applying a modification step if the middle result goes beyond the valid BCD range. This extra modification stage, however, adds noticeable propagation delay and increases hardware complexity. This paper introduces a high-speed, low-power CMOS-based BCD adder that embeds the correction logic directly into the core computational path, eliminating the need for a separate stage. The design employs a compact two-level architecture built around Netlist1 and Netlist2, which efficiently handle intermediate calculations and directly produce the final BCD sum and carry outputs. Implemented in 45 nm CMOS technology and thoroughly simulated in LTSpice-24 across multiple supply voltages, the circuit delivers strong results: average power dissipation of 399.423 pW at 1.5 V, rising to 579.034 pW at 1.8 V and 1129 pW at 2.5 V. The transistor count remains fixed at 366, yet the architecture still offers markedly better computational efficiency. Overall, the proposed BCD adder provides an excellent solution for high-speed, energy-efficient decimal arithmetic in today’s digital systems.
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