Low Power Application-based Flip-Flop for Static High Frequency for Hybrid Topology
Keywords:
18t topology, Flip-Flop, Low power design, Power efficient, power delay product (PDP).Abstract
Flip-Flops (FFs) are fundamental storage components that are widely employed in digital system designs that include several FF-rich modules, including register files, shift registers, and FIFOs, as well as intensive pipelining techniques. The FFs are utilised in typical digital system architecture and the power consumption of clock distribution networks. In order to achieve ultralow power consumption, this project suggests a true single-phase clocking FF circuit with just 19 transistors. The design has a hybrid logic architecture that integrates static-CMOS logic with complementary pass-transistor logic, and it adheres to a master-slave logic structure. In order to attain optimal power and delay performance, fewer transistors are used in the design through the use of a logic structure reduction approach. In order to prevent leakage power consumption, during operation, no internal nodes are left floating, despite the circuit's simplicity. To improve time performance, this design makes use of a virtual VDD design technique, which enables a quicker state shift in the slave latch. Transistor sizes are optimised in circuit implementation based on the power delay product (PDP).
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