Synthesis of Hidden State Transitions for Sequential Logic Locking

Abstract

This research presents a new high-speed counter design connected to an LFSR condition extension. With the suggested increase, 2m states may be accommodated by an m-bit LFSR number with 62 meters 1Ð stages without affecting counting performance because merely the low-order bits can frequently swapped, the suggested counter, which comprises two sub-counters, has a high counting rate and requires less hardware to convert a long-term sequential state into a binary state. We implement the traditional synchronous binary counter for the high-order sub-counter and build the suggested LFSR counter for the low-order sub-counter. Performance dropped due to the large fan-out of the second-order sub-counter, but the installed counter makes up for it. The suggested counter offers an accuracy rate independent of size and was constructed using conventional cells, functioning at 2.08 GB in a 65 nm CMOS process.