Power Optimized FPGA Implementation of High-Speed Test Pattern Generator for BIST
Keywords:
3-weight, Accumulator TPG, Bist, Clock gating, FF AND gate, Flipflop_CLK, FPGA, FSM controller, Fulladder, Response analyzer, Sa0 fault, Verilog HDL, Vivado, Artix-7Abstract
Pseudorandom Built-In Self-Test (BIST) schemes are essential for the efficient testing of Integrated Circuits (ICs), ensuring high-quality manufacturing yield. As modern integrated circuit complexity increases, test vector generation time and power consumption during testing become critical concerns. This paper presents an FPGA implementation of a BIST architecture featuring a Flip-Flop and AND gate (FF+AND) based clock-gating technique, an accumulator-based 3-weight Test Pattern Generator (TPG) using a Full Adder array, a 4-state finite state machine (FSM) BIST controller, and a combinational response analyser for fault detection. The clock gating is implemented through the Flipflop_Clk module, which combines a positive-edge-triggered D Flip-Flop (dff. v) with an AND gate to produce a glitch-free gated clock. The TPG employs ten FullAdder instances forming an accumulator with 3-weight masking via set_mask and reset_mask inputs, generating effective fault-covering patterns. The Circuit Under Test (CUT) implements a mixed logic network with AND, OR, XOR, and NAND gates with 10 inputs and 3 outputs. Implementation on Xilinx Artix-7 FPGA using Vivado achieves a total on-chip power of 0.59W, maximum delay of 5.496 ns, with only 46 Slice LUTs and 25 Slice Registers. The system correctly detects SA0 (stuck-at-0) faults on node N11, with the extension module (Extension.v) showing approximately 41.7% power reduction compared to the ungated Top.v baseline.
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