A Singular Approach for 1-Bit Novel Adder

Abstract

Adders are fundamental digital circuits that perform the addition of binary numbers. They are essential components in various Arithmetic operations within microprocessors, microcontrollers and other digital systems. The adders are the basic building blocks for most multi-bit adders, essential for arithmetic operations in digital systems. For this, we need to reduce the transistor count and delay. In this paper, we designed a 1-bit novel Adder using Micro wind 3.9 software and DSCH 3.9 software using CMOS technology. In the proposed design, we reduced transistor count, area, delay, and power delay product compared to the previous work. Some works are proposed on full adders to minimize the product's delay, area, and power delay. We observed that these works have drawbacks such as design complexity, sensitivity to circuit variations and limited performance improvement. We proposed "A SINGULAR APPROACH TO NOVEL 1-BIT ADDER" to eliminate this drawback. In this work, we observed that reducing the transistor count reduces delay, area, power, and Power delay products. By lowering the transistor count, we expect the following results to be observed: delay reduction, less design complexity, increment in performance improvement, decrement in power, area, and power delay product.