1.
Rashmitha Rani B.N., K.B. Ramesh. The Design and Micro-Architectural Performance Optimization of Parallel Adder Circuit. RTSST [Internet]. 2024 Jun. 5 [cited 2026 Jun. 23];:9-17. Available from: https://matjournals.net/engineering/index.php/RTSST/article/view/522