1.
Puram Vamshi, Mahesh Kumar N, Pratyush, R Harinandan. Design and Implementation of an 8-bit Universal Shift Register using Verilog. JOVDSP [Internet]. 2024 Aug. 17 [cited 2025 Oct. 24];10(2):27-30. Available from: https://matjournals.net/engineering/index.php/JOVDSP/article/view/836