Ch. Satya Surekha, B. Harshitha Sai, B. Amruthavalli, G. Bhargavi, Akula Mallaiah. Design and Optimization of a Monotonic Asynchronous Two-Bit Full Adder Using Majority Gate Logic for Low-Power Digital Systems. JOVDSP [Internet]. 2025 Apr. 14 [cited 2026 Jul. 14];11(1):27-35. Available from: https://matjournals.net/engineering/index.php/JOVDSP/article/view/1701