Ch. Satya Surekha, B. Harshitha Sai, B. Amruthavalli, G. Bhargavi, and Akula Mallaiah. “Design and Optimization of a Monotonic Asynchronous Two-Bit Full Adder Using Majority Gate Logic for Low-Power Digital Systems”. Journal of VLSI Design and Signal Processing, vol. 11, no. 1, Apr. 2025, pp. 27-35, https://matjournals.net/engineering/index.php/JOVDSP/article/view/1701.