Ch. Satya Surekha, B. Harshitha Sai, B. Amruthavalli, G. Bhargavi and Akula Mallaiah (2025) “Design and Optimization of a Monotonic Asynchronous Two-Bit Full Adder Using Majority Gate Logic for Low-Power Digital Systems”, Journal of VLSI Design and Signal Processing, 11(1), pp. 27–35. Available at: https://matjournals.net/engineering/index.php/JOVDSP/article/view/1701 (Accessed: 14 July 2026).