CH. SATYA SUREKHA; B. HARSHITHA SAI; B. AMRUTHAVALLI; G. BHARGAVI; AKULA MALLAIAH. Design and Optimization of a Monotonic Asynchronous Two-Bit Full Adder Using Majority Gate Logic for Low-Power Digital Systems. Journal of VLSI Design and Signal Processing, [S. l.], v. 11, n. 1, p. 27–35, 2025. Disponível em: https://matjournals.net/engineering/index.php/JOVDSP/article/view/1701. Acesso em: 16 apr. 2026.