[1]
Ch. Satya Surekha, B. Harshitha Sai, B. Amruthavalli, G. Bhargavi and Akula Mallaiah 2025. Design and Optimization of a Monotonic Asynchronous Two-Bit Full Adder Using Majority Gate Logic for Low-Power Digital Systems. Journal of VLSI Design and Signal Processing. 11, 1 (Apr. 2025), 27–35.