Efficient Implementation of FIR Filter Utilizing Dadda Multiplier and Brent Kung Adder

Abstract

In signal processing and communication systems, digital filters play a pivotal role, as they are one of the fundamental components of traditional DSP processors. The performance of digital filter multipliers and adders stands out, as they are essential for carrying out various mathematical operations. However, multipliers often dominate in terms of silicon space and power consumption, and adders incur delays. A novel technique for developing efficient FIR filters must be proposed to address this challenge. The primary objective is to achieve an optimal trade-off between power consumption and computational efficiency. By leveraging innovative design strategies, such as the Dadda multiplier, which enables concurrent processing of multiple bits and the Brent-Kung adder, which employs a carry look ahead strategy to minimize critical path delays and diminish power consumption, the performance of FIR filters can be enhanced in signal processing applications compared to regular adders. The proposed approach involves utilizing a Dadda multiplier and a Brent-Kung adder for the final stages of merging in the filter design. This combination aims to strike a balance between computational efficiency and power usage. To evaluate the system's effectiveness, it is implemented in Verilog HDL and compared against a Booth-encoded multiplier. This work underscores the importance of efficient hardware implementation in achieving high-performance digital signal processing systems.