International Journal of Digital Electronics and Microprocessor Technology

Performance Comparison of GaAs/Si3N4 Based Cylindrical Gate-All-Around FETs under sub-20nm Channel Lengths

2026-03-24T11:49:52+00:00

This study explores the potential of gallium arsenide (GaAs) as a channel material and silicon nitride (Si₃N₄) as the oxide material for cylindrical gate-all-around field-effect transistors (CGAA-FETs) for sub-20 nm channel lengths. The investigated CGAA FET has been designed and implemented in the Silvaco TCAD simulation framework using the ATLAS tool. The modelling of the FET includes quantum effects, non-equilibrium Green’s function formalism, as well as well-known physical models such as Schottky-Read-Hall and Auger recombination, field and concentration dependent mobility models and Fermi statistics for accuracy. Simulations demonstrate that GaAs-based CGAA-FETs can effectively mitigate short-channel effects (SCEs) even at sub-14 nm technology nodes. The superior material properties of GaAs, such as optimised band-gap, higher electron mobility and electron affinity, higher permittivity of Si₃N₄, and improved gate control of CGAA FET structure, contribute to reducing SCEs and improving the performance. These findings suggest that GaAs-based CGAA-FETs offer a promising solution for developing high-performance, SCE-free transistors for next-generation electronic devices.

Dynamic Speed Regulation and Performance Evaluation of a DC Motor using Pulse Width Modulation (PWM) Control

2026-04-23T11:17:50+00:00

This paper presents an experimental and analytical study of DC motor speed control using Pulse Width Modulation (PWM). Direct Current (DC) motors are extensively employed in industrial and automation systems because they provide superior speed control and operational flexibility. As modern industries increasingly demand higher efficiency and reduced energy consumption, effective motor speed regulation has become a critical requirement for improving overall system performance. In this context, this research explores the speed control of a DC motor through the implementation of the PWM technique, which is widely recognised for its accuracy and efficiency in power control applications. PWM operates by adjusting the duty cycle of a switching signal; consequently, the average voltage supplied to the motor can be regulated without significant power loss. By varying the duty cycle, the motor receives different effective voltage levels, and therefore its rotational speed can be controlled precisely. In this study, the behaviour and performance of a DC motor are examined under multiple duty cycle conditions ranging from 20% to 100%, enabling a comprehensive evaluation of the relationship between duty cycle variation and motor speed. Both experimental observations and simulation results indicate that the motor speed increases proportionally with the duty cycle, while the system continues to maintain efficient power utilisation and stable operation. Furthermore, the findings demonstrate that PWM-based control not only enhances speed regulation accuracy but also improves energy efficiency and system reliability. Consequently, PWM emerges as a highly effective and flexible technique for DC motor speed control, making it particularly suitable for modern industrial and automation applications.

Stroke Assist: A Smart System for Post-stroke Rehabilitation using IoT and Machine Learning

2026-05-11T05:44:25+00:00

Stroke is a leading cause of long-term disability and mortality, requiring continuous monitoring and timely intervention to prevent recurrent attacks. This study presents the design and implementation of a smart IoT-based health monitoring system for stroke patients that continuously tracks vital parameters such as oxygen levels, heartbeat, and body movements. The system integrates sensors, including an ECG, heartbeat sensor, and ADXL345 accelerometer with an ESP32 microcontroller, transmitting real-time data to the ThingSpeak cloud via Wi-Fi. A Python-based web application developed using Flask/Django retrieves and visualizes the data through ThingSpeak APIs, enabling caregivers and physicians to monitor patient health and recovery trends remotely. Furthermore, machine learning algorithms, including K-nearest neighbors (KNN), random forest, logistic regression, and support vector machine (SVM), are used to predict abnormal physiological conditions or potential health risks analyze historical data to predict stroke recurrence risks and recovery patterns, and provide early warnings for abnormal health conditions. The system also delivers personalized therapy recommendations based on analytical insights and triggers emergency alerts via Telegram during critical events. Experimental results demonstrate reliable real-time monitoring, accurate prediction of recovery trends, and timely alert generation. The proposed system offers a cost-effective, intelligent, and scalable platform for continuous post-stroke rehabilitation and proactive healthcare management.

Robust Indoor Localization using Wireless Signal Sensing and Data-driven Models

2026-05-12T06:52:49+00:00

Accurate indoor localization remains a challenging problem due to multipath propagation, signal attenuation, and dynamic environmental changes that degrade the reliability of traditional positioning techniques. This research presents a robust indoor localization framework that leverages wireless signal sensing and data-driven models to achieve high positioning accuracy in complex indoor environments. The proposed approach utilizes widely available wireless signals, such as Wi-Fi and Bluetooth, and extracts discriminative features from received signal measurements to construct an adaptive localization model. Advanced data-driven techniques, including machine learning and deep learning algorithms, are employed to capture nonlinear relationships between signal characteristics and spatial locations, enabling improved resilience to noise and environmental variability. Experimental evaluations conducted in diverse indoor scenarios demonstrate that the proposed method significantly outperforms conventional fingerprinting and model-based approaches. Results indicate an average localization accuracy improvement of 20–35%, with sub-meter positioning precision achieved in dense deployment settings. Furthermore, the system exhibits strong robustness to signal fluctuations and layout changes, maintaining stable performance over time with minimal recalibration. These results highlight the effectiveness of combining wireless signal sensing with data-driven modelling for reliable and scalable indoor localization applications.

Hardware Acceleration for Convolutional Neural Networks on Edge Devices: A Survey of FPGA-based Designs, Quantization, and Lightweight Architectures for Microcontroller Integration

2026-05-30T10:58:51+00:00

This literature survey investigates hardware acceleration techniques for convolutional neural networks (CNNs) targeting edge devices, with a specific emphasis on field-programmable gate array (FPGA)-based designs. The increasing computational complexity and memory demands of modern CNNs present significant challenges for deployment on resource-constrained edge platforms, necessitating specialized acceleration methods. This study systematically reviews recent academic contributions (2018–2024) focusing on optimization strategies, including INT8 quantization, architectural pruning, and the development of lightweight models (e.g., MobileNet, Tiny-YOLO). The efficiency of 3×3 convolution optimization, memory access bottlenecks, latency constraints, and the role of direct memory access (DMA)-based data transfer in mitigating these issues. A comparative analysis of various hardware platforms—GPUs, FPGAs, ASICs, and external accelerators—is provided, evaluating their performance, power consumption, flexibility, and cost in the context of edge AI. A critical review of existing FPGA-based convolution accelerators highlights their methodologies, advantages, and limitations, specifically addressing their applicability to low-cost microcontrollers. Identified research gaps include the high complexity and power consumption of current neural processing units (NPUs), their unsuitability for highly constrained microcontrollers, and inefficiencies in performing fundamental operations such as 3×3 convolutions. Based on this analysis, a novel, simple, and energy-efficient external convolution accelerator architecture is proposed. This architecture is dedicated to 3×3 convolutions, supports INT8 inputs with INT32 accumulation, employs parallel MAC units, and incorporates a DMA-based data transfer interface, all optimized for seamless integration with low-cost microcontrollers. This proposed design aims to offer reduced latency, ultra-low power consumption, and greater simplicity than full NPUs, making it highly suitable for diverse edge AI applications.